SA1110 Datasheet, PDF (86/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

System Control Module
9.2.1.4
Interrupt Controller Level Register (ICLR)
The interrupt controller level register (ICLR) controls whether a pending interrupt generates an
FIQ or an IRQ CPU interrupt. If a pending interrupt is unmasked, the corresponding ICLR bit field
is decoded to select which CPU interrupt should be asserted. If the interrupt is masked, then the
corresponding bit in the ICLR has no effect. The following table shows the location of all interrupt
level bits in the ICLR; question marks indicate that the values are unknown at reset.
0h 9005 0008
ICLR
Read/Write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
Bits
Name
Description
Interrupt level n (where n = 0 through 31).
n
ILn
0 – Interrupt routed to CPU IRQ interrupt input.
1 – Interrupt routed to CPU FIQ interrupt input.
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SA-1110 Developer’s Manual