SA1110 Datasheet, PDF (211/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Peripheral Control Module
The following table shows the location of all 10 bit-fields located in LCD control register 0
(LCCR0). The user must program the control bits within all other control registers before setting
LEN=1 (a word write can be used to configure LCCR0 while setting LEN after all other control
registers have been programmed), and also must disable the LCD controller when changing the
state of any control bit within the LCD controller. Note that writes to reserved bits are ignored and
reads return zeros.
0h B010 0000
LCCR0: LCD Control Register 0
Read/Write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
PDD
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
(Sheet 1 of 2)
Bits
Name
Description
LCD controller enable.
0
LEN
0 – LCD controller disabled. Control of L_PCLK, L_LCLK, L_FCLK, L_BIAS, and the LDD
7:0 pins is given to the PPC unit to be used as general-purpose I/O pins.
1 – LCD controller enabled.
Color/monochrome select.
1
CMS
0 – Color operation enabled.
1 – Monochrome operation enabled.
Single-/dual-panel display select.
0 – Single-panel display enabled. LDD 3:0 used for monochrome, LDD 7:0 used for color.
1 – Dual-panel display enabled. LDD 7:0 used for monochrome, LDD 7:0 and GPIO 9:2
2
SDS
used for color (user must also program GPDR and GAFR registers within the GPIO unit).
Note: SDS is ignored in active mode (PAS=1). For dual-panel operation, the user must
disable the LCD, set SDS, program the upper panel DMA base address, program the lower
panel DMA base address, and enable the LCD.
LCD disable done mask.
3
LDM
0 – LCD disable done condition generates an interrupt (state of LDD status sent to the
interrupt controller).
1 – LCD disable done condition does not generate an interrupt (LDD status bit ignored).
Base address update mask.
4
BAM
0 – Base address update condition generates an interrupt (state of BAU status sent to the
interrupt controller).
1 – Base address update condition does not generate an interrupt (BAU status bit ignored).
Error mask.
0 – Bus error and FIFO over/underrun errors generate an interrupt (state of BER, IOL, IUL,
5
ERM
IOU, IUU, OOL, OUL, OUU status sent to the interrupt controller).
1 – Bus error and FIFO over/underrun errors do not generate an interrupt (BER, IOL, IUL,
IOU, IUU, OOL, OUL, OOU, OUU status bits ignored).
6
—
Reserved.
Passive/active display select.
7
PAS
0 – Passive or STN display operation enabled. Dither logic is enabled.
1 – Active or TFT display operation enable. Dither logic bypassed, pin timing changes to
support continuous pixel clock, output enable, VSYNC, HSYNC signals.
SA-1110 Developer’s Manual
11-31