SA1110 Datasheet, PDF (9/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

11.8.1.1 Signalling Levels.................................................................................. 11–56
11.8.1.2 Connecting the USB to the SA-1110 ................................................... 11–57
11.8.1.3 Bit Encoding ........................................................................................ 11–58
11.8.1.4 Field Formats....................................................................................... 11–59
11.8.1.5 Packet Formats ...................................................................................11–60
11.8.1.6 Transaction Formats............................................................................11–61
11.8.1.7 UDC Device Requests......................................................................... 11–62
11.8.2 UDC Register Definitions........................................................................... 11–63
11.8.3 UDC Control Register ................................................................................ 11–63
11.8.3.1 UDC Disable (UDD)............................................................................. 11–64
11.8.3.2 UDC Active (UDA) ............................................................................... 11–64
11.8.3.3 Resume Interrupt Mask (RESM) .........................................................11–65
11.8.3.4 Endpoint 0 Interrupt Mask (EIM).......................................................... 11–65
11.8.3.5 Receive Interrupt Mask (RIM)............................................................. 11–65
11.8.3.6 Transmit Interrupt Mask (TIM) ............................................................ 11–65
11.8.3.7 Suspend Interrupt Mask (SUSM).........................................................11–65
11.8.3.8 Software Control of the UDC ...............................................................11–66
11.8.4 UDC Address Register .............................................................................. 11–67
11.8.5 UDC OUT Max Packet Register ................................................................ 11–67
11.8.6 UDC IN Max Packet Register .................................................................... 11–68
11.8.7 UDC Endpoint 0 Control/Status Register................................................... 11–68
11.8.7.1 OUT Packet Ready (OPR) .................................................................. 11–68
11.8.7.2 IN Packet Ready (IPR) ........................................................................ 11–68
11.8.7.3 Sent Stall (SST) ...................................................................................11–68
11.8.7.4 Force Stall (FST) ................................................................................. 11–68
11.8.7.5 Data End (DE) ..................................................................................... 11–69
11.8.7.6 Setup End (SE).................................................................................... 11–69
11.8.7.7 Serviced OPR (SO) ............................................................................. 11–69
11.8.7.8 Serviced Setup End (SSE) .................................................................. 11–69
11.8.8 UDC Endpoint 1 Control/Status Register................................................... 11–70
11.8.8.1 Receive FIFO Service (RFS) ...............................................................11–70
11.8.8.2 Receive Packet Complete (RPC) ........................................................ 11–71
11.8.8.3 Receive Packet Error (RPE) ................................................................ 11–71
11.8.8.4 Sent Stall (SST) ...................................................................................11–71
11.8.8.5 Force Stall (FST) ................................................................................. 11–71
11.8.8.6 Receive FIFO Not Empty (RNE).......................................................... 11–71
11.8.9 UDC Endpoint 2 Control/Status Register................................................... 11–72
11.8.9.1 Transmit FIFO Service (TFS) .............................................................. 11–72
11.8.9.2 Transmit Packet Complete (TPC)........................................................ 11–72
11.8.9.3 Transmit Packet Error (TPE) .............................................................. 11–73
11.8.9.4 Transmit Underrun (TUR) .................................................................... 11–73
11.8.9.5 Sent STALL (SST) ............................................................................... 11–73
11.8.9.6 Force STALL (FST) ............................................................................. 11–73
11.8.10 UDC Endpoint 0 Data Register.................................................................. 11–74
11.8.11 UDC Endpoint 0 Write Count Register ...................................................... 11–75
11.8.12 UDC Data Register .................................................................................... 11–75
11.8.13 UDC Status/Interrupt Register ................................................................... 11–76
11.8.13.1 Endpoint 0 Interrupt Request (EIR) ..................................................... 11–76
11.8.13.2 Receive Interrupt Request (RIR) .........................................................11–76
11.8.13.3 Transmit Interrupt Request (TIR).........................................................11–77
11.8.13.4 Suspend Interrupt Request (SUSIR) ................................................... 11–77
11.8.13.5 Resume Interrupt Request (RESIR) .................................................... 11–77
11.8.13.6 Reset Interrupt Request (RSTIR) ....................................................... 11–77
SA-1110 Developer’s Manual
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