SA1110 Datasheet, PDF (245/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Peripheral Control Module
11.8.3.3
Resume Interrupt Mask (RESM)
The resume interrupt mask (RESM) bit masks or enables the resume interrupt request. When
RESM=1, the interrupt is masked, and the RESIR bit in the status/interrupt register is not allowed
to be set. When RESM=0, the interrupt is enabled. Whenever a suspend condition occurs, the
RESIR bit is set.
Note: Programming RESM=1 does not affect the current state of RESIR. It only blocks future
zero–to–one transitions of RESIR.
11.8.3.4
Endpoint 0 Interrupt Mask (EIM)
The endpoint 0 interrupt mask (EIM) bit is used to mask or enable the endpoint 0 interrupt request.
When EIM=1, the interrupt is masked and the EIR bit in the status/interrupt register is not allowed
to be set. When EIM=0, the interrupt is enabled, and whenever an interruptible condition occurs in
the receiver, the EIR bit is set.
Note: Programming EIM=1 does not affect the current state of EIR. It only blocks future zero–to–one
transitions of EIR.
11.8.3.5
Receive Interrupt Mask (RIM)
The receive interrupt mask (RIM) bit is used to mask or enable the receive FIFO service request
interrupt. When RIM=1, the interrupt is masked and the RIR bit in the status/interrupt register is
not allowed to be set. When RIM=0, the interrupt is enabled, and whenever an interruptible
condition occurs in the receiver, the RIR bit is set.
Note: Programming RIM=1 does not affect the current state of RIR. It only blocks future zero to one
transitions of RIR.
11.8.3.6
Transmit Interrupt Mask (TIM)
The transmit interrupt mask (TIM) bit is used to mask or enable the transmit endpoint 2 interrupt
request. When TIM=1, the interrupt is masked and the TIR bit in the status/interrupt register is not
allowed to be set. When TIM=0, the interrupt is enabled, and whenever an interruptible condition
occurs in the transmitter, the TIR bit is set.
Note: Programming TIM=1 does not affect the current state of TIR. It only blocks future zero to one
transitions of TIR.
11.8.3.7
Suspend Interrupt Mask (SUSM)
The suspend interrupt mask (SUSM) bit masks or enables the suspend interrupt request. When
SUSM=1, the interrupt is masked, and the SUSIR bit in the status/interrupt register is not allowed
to be set. When SUSM=0, the interrupt is enabled. Whenever a suspend condition occurs, the
SUSIR bit is set.
Note: Programming SUSM=1 does not affect the current state of SUSIR. It only blocks future
zero–to–one transitions of SUSIR.
SA-1110 Developer’s Manual
11-65