SA1110 Datasheet, PDF (143/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Memory and PCMCIA Control Module
10.4 Dynamic Interface Operation
This section describes the dynamic memory interface.
10.4.1 DRAM Overview
The dynamic memory interface supports up to four banks, organized as two bank pairs. Both banks
within a pair must have the same DRAM size, configuration, timing type, and data bus width.
Initialization software must set up the memory interface configuration registers with the DRAM
timing type, data bus width, number of row address bits, nCAS/DQM waveforms, and timing
parameters. The SA-1110 generates accesses of 1-8 words.
Table 10-6 shows some of the supported DRAM configurations.
Table 10-6. Some DRAM Memory Size Options
Bank Size
(Mbyte/Bank)
DRAM
Configuration
(Words x Bits)
Chip Size
Number Chips /
Bank
Row bits x
Column Bits
Maximum
Memory
(4 Banks,
32-bit Bus)
Total Number
of Chips
16-bit
Bus
512
Kbyte
1
Mbyte
2
Mbyte
2
Mbyte
4
Mbyte
8
Mbyte
8
Mbyte
32-bit
Bus
1
Mbyte
2
Mbyte
4
Mbyte
4
Mbyte
8
Mbyte
16
Mbyte
16
Mbyte
256 K x 16
512 K x 8
1Mx4
1 M x 16
2Mx8
4Mx4
4 M x 16
16
Mbyte
32
Mbyte
32
Mbyte
64
Mbyte
128
Mbyte
32
Mbyte
64
Mbyte
64
Mbyte
128
Mbyte
N/A
8Mx8
16 M x 4
16 M x 16
32 M x 8
64 M x 4
4 Mbit
4 Mbit
16-bit
Bus
1
2
32-bit
Bus
2
4
9x9
10 x 8
10 x 9
4Mbit
4
8
10 x 10
16 Mbit
1
16 Mbit
2
16 Mbit
4
64 Mbit
1
64 Mbit
2
64 Mbit
4
256 Mbit 1
2
10 x 10
12 x 8
4
11 x 10
12 x 9
8
11 x 11
12 x 10
2
11 x 11
12 x 10
13 x 9
14 x 8
4
12 x 11
13 x 10
14 x 9
8
12 x 11
13 x 11
14 x 10
2
15 x 9
256 Mbit 2
4
15 x 10
256 Mbit 4
N/A
15 x 11
16-bit 32-bit
Bus
Bus
2
Mbyte
4
Mbyte
8
Mbyte
8
Mbyte
16
Mbyte
32
Mbyte
32
Mbyte
4
Mbyte
8
Mbyte
16
Mbyte
16
Mbyte
32
Mbyte
64
Mbyte
64
Mbyte
16-bit 32-bit
Bus Bus
4
8
8
16
16
32
4
8
8
16
16
32
4
8
64
128
8
16
Mbyte Mbyte
128 256
16
32
Mbyte Mbyte
128 256
4
8
Mbyte Mbyte
256 512
8
16
Mbyte Mbyte
512 N/A
Mbyte
16
N/A
Table 10-7 shows the DRAM row/column address multiplexing. For each row size, RAS time to
CAS time address bit changes only occur if they are required; all other bits (including A 25 and
A 9:0 bits not shown here) remain driven by the corresponding internal address bits throughout the
transfer. Column address sizes of 12, 11, 10, 9, and 8 are supported if three conditions are met:
SA-1110 Developer’s Manual
10-29