SA1110 Datasheet, PDF (80/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

System Control Module
9.1.2.1
9.1.3
3.6864 MHz Option for GP 27 Alternate Output Function
When GP 27 is configured for its alternate output function by setting bit 27 in both the GAFR and
GPDR, bit 29 of the test unit control register (TUCR) at physical address 0x9003 0008 can be set to
select the 3.6864 MHz oscillator output instead of the 32.768 KHz oscillator output. When
TUCR 29 is cleared the 32.768 KHz oscillator output is selected again. Neither option provides a
fixed phase relationship with any other pin signals; and some glitching may occur when switching
between the two options.
The 3.6864 MHz option is particularly useful for companion chips that require some clock cycles
after assertion of VDD_FAULT or BATT_FAULT. The oscillator output will continue through the
first step of the sleep shutdown sequence, which lasts for one cycle of the power manager’s 32.768
KHz clock (~30 microseconds). Thus, at least 112 cycles of 3.6864 MHz oscillation are provided
prior to shutdown. See Section 9.5.3 for a detailed description of sleep mode and the sleep
shutdown sequence.
GPIO Register Locations
The following table shows the registers associated with the GPIO block and the physical addresses
used to access them.
Address
0h 9004 0000
0h 9004 0004
0h 9004 0008
0h 9004 000C
0h 9004 0010
0h 9004 0014
0h 9004 0018
0h 9004 001C
Name
GPLR
GPDR
GPSR
GPCR
GRER
GFER
GEDR
GAFR
Description
GPIO pin-level register
GPIO pin direction register
GPIO pin output set register
GPIO pin output clear register
GPIO rising-edge detect register
GPIO falling-edge detect register
GPIO edge detect status register
GPIO alternate function register
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SA-1110 Developer’s Manual