SA1110 Datasheet, PDF (329/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Peripheral Control Module
11.12.6.16 Telecom Codec Enabled Flag (TCE) (read-only, noninterruptible)
The telecom codec enabled (TCE) flag indicates when the telecom codec input and/or output is
enabled, which in turn, indicates that the telecom sample rate counter is enabled. This flag is set
after the following sequence occurs: a register write command is issued to Telecom Control
Register B (register 6), and either bit 14 or 15 is set (tel_in_ena or tel_out_ena) by writing to
MCDR2; the write command is sent to the codec via subframe 0; the data value is latched within
codec register 6; and SFRM is asserted to indicate the start of the next frame. TCE is automatically
cleared using the same sequence with the exception that bits 14 and 15 are cleared, disabling both
the input and output paths of the telecom codec. This bit does not request an interrupt.
The following table shows the bit locations corresponding to the status and flag bits within the
MCP status register. MCSR contains a collection of read/write, read-only, interruptible, and
noninterruptible bits (refer to the bit descriptions above). Writes to read-only bits have no effect.
The user must clear set status bits before enabling the MCP. Note that writes to reserved bits are
ignored and reads return zeros; question marks indicate that the values are unknown at reset.
0h 8006 0018
MCP Status Register: MCSR
Read/Write and Read-Only
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
000000000000000000000101????0000
(Sheet 1 of 2)
Bits
Name
Description
Audio transmit FIFO service request flag (read-only).
0 – Audio transmit FIFO is more than half-full (five or more entries filled) or MCP disabled.
0
ATS
1 – Audio transmit FIFO is half-full or less (four or fewer entries filled) and MCP operation is
enabled, DMA service request signalled, interrupt request signalled if not masked (if
ATE=1).
Audio receive FIFO service request (read-only).
0 – Audio receive FIFO is less than half-full (three or fewer entries filled) or MCP disabled.
1
ARS
1 – Audio receive FIFO is half-full or more (four or more entries filled) and MCP operation is
enabled, DMA service request signalled, interrupt request signalled if not masked (if
ARE=1).
Telecom transmit FIFO service request flag (read-only).
0 – Telecom transmit FIFO is more than half-full (five or more entries filled) or MCP
2
TTS
disabled.
1 – Telecom transmit FIFO is half-full or less (four or fewer entries filled) and MCP
operation is enabled, DMA service request signalled, interrupt request signalled if not
masked (if TTE=1).
Telecom receive FIFO service request (read-only).
0 – Telecom receive FIFO is less than half full (three or fewer entries filled) or MCP
3
TRS
disabled.
1 – Telecom receive FIFO is half full or more (four or more entries filled) and MCP
operation is enabled, DMA service request signalled, interrupt request signalled if not
masked (if TRE=1).
Audio transmit FIFO underrun.
4
ATU
0 – Audio transmit FIFO has not experienced an underrun.
1 – Audio transmit logic attempted to fetch data from transmit FIFO while it was empty
request interrupt.
SA-1110 Developer’s Manual
11-149