SA1110 Datasheet, PDF (141/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Memory and PCMCIA Control Module
0h A000 0030
SMCNFG
Read/Write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved
Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 1 1 0 0 ? ? ? ? ? 1 0 0 ? ? 0 *
* Upon hardware or sleep reset, SM0 is set to the value of the SMROM_EN pin.
(Sheet 2 of 3)
Bits
15
17..16
19..18
22..20
27..23
30..28
Name
RL0
SM3..2
—
RA2 2..0
—
CL2 2..0
Description
RAS latency for bank pair 0/1.
It is the RAS-to-CAS delay (number of external SDCLK cycles between ACT command and
READ command). The unit size for RL0 is the external SDCLK cycle: when SMROM is run
at half the memory clock frequency (MDREFR:K0DB2 = 1), the delay is 2*RL0 internal
memory cycles.
See Section 10.3.1 for description of the software sequence required whenever changing
the RAS latency.
0 - 1 clock.
1 - 2 clock.
Hardware or sleep reset forces RL0=1. If SMROM_EN=1, RL0 must be maintained at this
value to avoid a mismatch in RAS latency between the SA-1110 and boot SMROM following
a subsequent hardware or sleep reset.
SMROM enables for bank 3 (bit 17) and bank 2 (bit 16).
0 - Bank is not SMROM enabled.
1 - Bank is SMROM enabled.
Reserved.
SMROM row address bit count for bank pair 2/3.
0xx - Reserved.
100 - 13 row address bits, supports 13x11, 13x10, 13x9, 13x8.
101 - Reserved.
11x - Reserved.
See Table 10-7 for a description of DRAM or SMROM row/column address multiplexing.
Reserved.
CAS latency for bank pair 2/3.
It is the number of external SDCLK cycles between reception of the READ command and
latching of the data. The unit size for CL2 is the external SDCLK cycle: when SMROM is
run at half the memory clock frequency (MDREFR:K0DB2 = 1), the delay is 2*CL2 internal
memory cycles.
000 - Reserved.
001 - 2 clocks.
010 - 3 clocks.
011 - 4 clocks.
100 - 5 clocks.
101 - 6 clocks.
110 - 7 clocks.
111 - Reserved.
SA-1110 Developer’s Manual
10-27