SA1110 Datasheet, PDF (104/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

System Control Module
Table 9-3.
• Type 7 – These pins are inputs and are actively sampled during sleep.
• Type 8 – These pins are inputs and are not observed during sleep; the receiver is disabled.
• Type 9 – These pins are analog inputs and outputs, and are always active.
Pin State During Sleep
Pin Name
Type Pin Name
A 25:0
1b
D 31:0
1b
nCS 5:0
2
RDY
8
nOE
2
nWE
2
nRAS/nSDCS 3:0 1
nCAS/DQM 3:0
1
nSDRAS
2b
nSDCAS
2b
nSDCKE[1:0]
1b
nSDCLK[2:0]
1b
RD/nWR
1b
nPOE
2
nPWE
2
nPIOW
2
nPIOR
nPCE 2:1
nIOIS16
nPWAIT
PSKTSEL
nPREG
L_DD 7:0
L_FCLK
L_LCLK
L_PCLK
L_BIAS
TXD_C
RXD_C
SCLK_C
SFRM_C
UDC+
Type Pin Name
2
UDC-
2
TXD_1
8
RXD_1
8
TXD_2
1b RXD_2
1b TXD_3
4
RXD_3
4
GP 27:0
4
SMROM_EN
4
ROM_SEL
4
PXTAL
4
PEXTAL
4
TXTAL
4
TEXTAL
4
PWR_EN
4
BATT_FAULT
Type Pin Name
4
VDD_FAULT
4
nRESET
4
nRESET_OUT
4
nTRST
4
TDI
4
TDO
4
TMS
3
TCK
8
TCK_BYP
8
TESTCLK
9
VDD
9
VDDX
9
VSS
9
VSSX
5
—
7
—
Type
7
7
1b
8
8
6
8
8
7
7
—
—
—
—
—
—
9.5.7
9.5.7.1
Power Manager Registers
The power manager is controlled through eight 32-bit registers. The power manager control
register (PMCR) is used to allow software invocation of sleep mode. The sleep status register
(PSSR) contains status bits that indicate why sleep mode was invoked. The power manager scratch
pad register (PSPR) is a general-purpose register used to store processor data during sleep. The
power manager wake-up enable register (PWER) is used to program the desired wake-up sources
in the system. The power manager general configuration register (PCFR) contains bits used to
control various configurable functions within the SA-1110. The power manager PLL configuration
register (PPCR) allows the user to change the PLL operating frequency. The power manager GPIO
sleep state register (PGSR) is used to program the value loaded onto GPIO outputs when the
SA-1110 transitions into sleep mode. The power manager oscillator status register (POSR) contains
a single bit that indicates whether the 32.768-kHz oscillator has stabilized after a hardware reset.
Power Manager Control Register (PMCR)
Sleep mode is invoked by setting the force bit within the power manager control register (PMCR).
The force bit is automatically cleared upon exiting sleep mode or when a hardware reset occurs.
Writing zero to the force bit has no effect. For reserved bits, writes are ignored and reads return
zero. This register should be protected by programming MMU permissions. The following table
shows the PMCR.
9-34
SA-1110 Developer’s Manual