SA1110 Datasheet, PDF (101/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

System Control Module
9.5.3.7
9.5.4
9.5.5
sequence, and subsequently negate the internal reset signal. This causes the SA-1110 to perform a
normal boot sequence because all information about the previous sleep state is lost.
Reviving the DRAMs from Self-Refresh Mode
Because the DRAMs are placed in self refresh prior to the sleep mode shutdown, their contents are
preserved during sleep. After exiting sleep, software must reconfigure the DRAM control registers,
which lost power during sleep mode, and then take the DRAMs out of self-refresh mode. Clearing
the DRAM hold (DH) bit in the power management status register (PMSR) will cause the
nRAS/nSDCS 3:0 and nCAS/DQM 3:0 pins to return to the negated state (high) in preparation for
a DRAM access.
In addition to clearing PMSR:DH, bringing SDRAM out of self-refresh requires that the SDRAM
controller be transitioned from a self-refresh and clock-stop state to an idle state. This involves
successive writes to the DRAM Refresh Control Register (MDREFR) to set one or both SDRAM
clock run bits (K1RUN and/or K2RUN) and to set the SDRAM clock enable bit (E1PIN). See the
Chapter 10, “Memory and PCMCIA Control Module” for details.
Notes on Power Supply Sequencing
On the SA-1110, as on the SA-110, it is important that VDDX (3.3 V nominal) power-up occur
before VDDI (1.5 V nominal). One approach to ensuring this sequencing is to power the 1.5-V
supply using the 3.3-V supply.
On the SA-1110, a second simple option is available. If the PWR_EN output is used to enable the
1.5-V supply, the SA-1110 will enforce the required sequencing by holding PWR_EN deasserted
until the 3.3-V supply is sufficiently high.
Assumed Behavior of an Intel^® StrongARM SA-1110 System
in Sleep Mode
The assumed model of an SA-1110 system in sleep mode is one in which the system is relatively
quiet. In particular, there should be no gratuitous switching on of the SA-1110 input pins. Although
there will be some switching in GPIOs to bring the processor out of sleep and potentially on the
VDD_FAULT and BATT_FAULT pins, the switching is a low-frequency activity and usually
brings the SA-1110 out of sleep mode.
The major concern is for power dissipation in sleep and requirements for the power supplies on the
processor during sleep. The SA-1110 generates these supplies using several on-chip regulators with
limited current capacity. Excessive activity on-chip pins might load these regulators beyond their
capacity and result in droop of the on-chip supplies.
One example is that of a component tied to one of the GPIO pins that constantly transmits to the
processor. If the system design indicated that activity from this detector should not bring the
SA-1110 out of sleep, the transitions from this GPIO might result in switching in the processor that
would exceed the sleep current limit.
This concern exists regardless of whether the GPIO is enabled as a wake-up source. Figure 9-3
shows the three power-related modes of the SA-1110 and the actions that cause transitions between
the modes.
SA-1110 Developer’s Manual
9-31