SA1110 Datasheet, PDF (177/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Memory and PCMCIA Control Module
10.7
Timing parameters are in memory clock cycle units. All are minimums except as noted:
Address access time:
6*(BS_xx+1) + 1
half-word or first byte FAST=0
5*(BS_xx+1)
second byte
FAST=0
4*(BS_xx+1) + 1
half-word or first byte FAST=1
4*(BS_xx+1)
second byte
FAST=1
Command (nPOE, nPWE, nPIOR, nPIOW) assertion time: 3*(BS_xx+1)
Address setup to command assert:
3*(BS_xx+1) + 1
half-word or first byte FAST=0
2*(BS_xx+1)
second byte
FAST=0
1*(BS_xx+1) + 1
half-word or first byte FAST=1
1*(BS_xx+1)
second byte
FAST=1
Address hold after command deassertion: BS_xx+1
nPWAIT valid after command assertion (max): 2*(BS_xx+1) - 2
Chip enable (nPCE1,2) setup to nPOE, nPWE assert:
3*(BS_xx+1) + 1
FAST=0
1*(BS_xx+1) + 1
FAST=1
Chip enable (nPCE1,2) setup to nPIOR, nPIOW assert:
3*(BS_xx+1) + 1 - (nIOIS16 delay from address)
half-word or first byte
2*(BS_xx+1) - (nIOIS16 delay from address)
second byte
1*(BS_xx+1) + 1 - (nIOIS16 delay from address)
half-word or first byte
1*(BS_xx+1) - (nIOIS16 delay from address)
second byte
Chip enabled hold from command deassert: BS_xx+1
FAST=0
FAST=0
FAST=1
FAST=1
See Chapter 13, “AC Parameters” for actual AC timing.
Memory Interface Reset and Initialization
On hardware or sleep reset, the dynamic memory interface is disabled. The boot ROM (connected
to nCS0) is configured for SMROM if SMROM_EN=1. Otherwise, boot ROM is configured for
the slowest nonburst ROM/Flash. The ROM_SEL pin determines the bus size of asynchronous
boot ROM. Immediately, boot ROM is available for reading and all memory interface control
registers are available for reading and writing.
On hardware reset the memory pins and controller are in the following state:
nRAS/nSDCS(3:0) = 0xF
nCAS/DQM(3:0) = 0xF
nCS(5:0) = 0xF
nOE = 1
nWE = 1
RD/nWR = 0
nPIOR = 1
nPIOW = 1
nPOE = 1
nPWE = 1
nSDRAS = 1
nSDCAS = 1
SDCKE 0 = SMROM_EN, SDCKE 1 = 0
if SMROM_EN=1, SDCLK 0 oscillating at one-half the memory clock frequency
(one-fourth the CPU frequency)
SA-1110 Developer’s Manual
10-63