SA1110 Datasheet, PDF (297/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Peripheral Control Module
clocking data through the serial shifter. Once the TBY bit becomes zero, the BRK bit can be negated,
and data is once again fetched from the transmit FIFO. Break does not affect the receive portion of the
FIFO; normal operation on the receive line continues during the signalling of a break.
11.11.5.4
Receive FIFO Interrupt Enable (RIE)
The receive FIFO interrupt enable (RIE) bit is used to mask or enable both the receive FIFO service request
interrupt and receiver idle interrupt. When RIE=0, the interrupts are masked and the receive FIFO service
request (RFS) and receiver idle status (RID) bits are ignored by the interrupt controller. When RIE=1, the
interrupts are enabled and whenever RFS or RID is set (one), an interrupt request is made to the interrupt
controller. Note that programming RIE=0 does not affect the current state of RFS or RID nor the receive
logic’s ability to set and clear these bits; it only blocks the generation of the interrupt request. Also note that
RIE does not affect generation of the receive FIFO DMA request that is asserted whenever RFS=1.
11.11.5.5 Transmit FIFO Interrupt Enable (TIE)
The transmit FIFO interrupt enable (TIE) bit is used to mask or enable the transmit FIFO service
request interrupt. When TIE=0, the interrupt is masked and the state of the transmit FIFO service
request (TFS) bit is ignored by the interrupt controller. When TIE=1, the interrupt is enabled, and
whenever TFS is set (one), an interrupt request is made to the interrupt controller. Note that
programming TIE=0 does not affect the current state of TFS nor the transmit FIFO logic’s ability to
set and clear TFS; it only blocks the generation of the interrupt request. Also note that TIE does
not affect generation of the transmit FIFO DMA request that is asserted whenever TFS=1.
11.11.5.6 Loopback Mode (LBM)
The loopback mode (LBM) bit is used to enable and disable the ability of the UART transmit and
receive logic to communicate. When LBM=0, the UART operates normally. The transmit and receive
data paths are independent and communicate via their respective pins. When LBM=1, the output of
the transmit serial shifter is directly connected to the input of the receive serial shifter internally, and
control of the TXD3 and RXD3 pins is given to the peripheral pin control (PPC) unit.
The following table shows the bit location of the bits within UART control register 3. RXE and
TXE are the only control bits that are reset to a known state to ensure the UART is disabled
following a reset of the SA-1110. The reset state of all other control bits is unknown (indicated by
question marks) and must be initialized before enabling the UART. Note that UTCR3 is the only
control register that may be written while the UART is enabled. Also note that writes to reserved
bits are ignored and reads return zeros.
Reset
0h 8005 000C
7
6
Reserved
0
0
Bits
Name
0
RXE
1
TXE
UTCR3
Read/Write
5
4
3
2
1
LBM
TIE
RIE
BRK
TXE
?
?
?
?
0
(Sheet 1 of 2)
Description
Receiver enable.
0 – UART receive operation disabled; PPC is given control of RXD3.
1 – UART receive operation enabled.
Transmitter enable.
0 – UART transmit operation disabled; PPC is given control of TXD3.
1 – UART transmit operation enabled.
0
RXE
0
SA-1110 Developer’s Manual
11-117