SA1110 Datasheet, PDF (49/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Coprocessors
5.2.5
5.2.6
Register 4 – RESERVED
Accessing register 4 may yield unpredictable results.
Register 5 – Fault Status
Reading register 5 returns the current contents of the fault status register (FSR). The FSR is written
when a data memory fault occurs or can be written by an MCR to the FSR. It is not updated for a
prefetch fault. See Chapter 7, “Memory Management Unit (MMU)” for more details. Bits 31:10
are undefined on read, ignored on write. Bit 9 is set when a data breakpoint is taken and can be
cleared by an MCR operation. Bit 8 is ignored on write and is always returned as zero. Refer to the
ARM Architecture Reference for a description of the domain and status fields.
Register 5 – Fault Status
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Undefined
D 0 Domain
Status
5.2.7
Register 6 – Fault Address
Reading register 6 returns the current contents of the fault address register (FAR). The FAR is
written when a data memory fault occurs with the virtual address of the data fault or can be written
by an MCR to the FAR.
Register 6– Fault Address
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Fault Virtual Address
5.2.8
Register 7 – Cache Control Operations
Register 7 is a write-only register. The CRm and OPC_2 fields are used to encode the cache control
operations. Operation for all other values for OPC_2 and CRm is unpredictable.
Function
Flush I+D
Flush I
Flush D
OPC_2
0b000
0b000
0b000
CRm
0b0111
0b0101
0b0110
Ignored
Ignored
Ignored
Data
SA-1110 Developer’s Manual
5-5