SA1110 Datasheet, PDF (152/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Memory and PCMCIA Control Module
Figure 10-9. SDRAM 1-Beat Read/Write Timing for 4 Bank x 4 M x 4 Bit Organization
(64 Mbit) at Half-Memory Clock Frequency (MDREFR:KnDB2=1))
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
CPU Clock
(2*TDL)+TRP+2
Trcd
2* TDL
TRP+1
Trcd
Memory
Clock
SDCLK
SDCKE
command
ACT
nRAS/nSDCS
READAP
ACT
WRITEAP
nSDRAS
nSDCAS
DRA13-12
Bank
DRA11
Row
DRA10
Row
DRA9-0
Col
nWE
RD/nWR
Bank
Row
Row
Row
Col
nCAS/DQM
D
D0
D0
Contents of DRAM register fields:
last
time
first
MDCNFG:DTIM0=1 MDCNFG:DWID0=0 MDCAS00=0101 0101 0101 0101 0101 0101 0111 1111(binary)
MDCNFG:DRAC0=5 MDCNFG:CDB20=0 MDCNFG:TRP0=1 MDCNGF:TDL0=2 MDCNFG:TWR0=3
A6700-02
10-38
SA-1110 Developer’s Manual