SA1110 Datasheet, PDF (4/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

5.2.11 Registers 10 – 12 RESERVED...................................................................... 5–7
5.2.12 Register 13 – Process ID Virtual Address Mapping ...................................... 5–7
5.2.13 Register 14 – Debug Support (Breakpoints).................................................. 5–7
5.2.14 Register 15 – Test, Clock, and Idle Control ................................................... 5–9
6
Caches, Write Buffer, and Read Buffer ...................................................................... 6–1
6.1 Instruction Cache (Icache) ................................................................................ 6–1
6.1.1 Icache Operation ........................................................................................... 6–1
6.1.2 Icache Validity ............................................................................................... 6–1
6.1.2.1 Software Icache Flush ............................................................................. 6–1
6.1.3 Icache Enable/Disable and Reset ................................................................. 6–2
6.1.3.1 Enabling the Icache ................................................................................. 6–2
6.1.3.2 Disabling the Icache ................................................................................ 6–2
6.2 Data Caches (Dcaches) .................................................................................... 6–2
6.2.1 Cacheable Bit – C.......................................................................................... 6–3
6.2.1.1 Cacheable Reads – C = 1 ....................................................................... 6–3
6.2.1.2 Noncacheable Reads – C = 0 ................................................................. 6–3
6.2.2 Bufferable Bit – B........................................................................................... 6–3
6.2.3 Software Dcache Flush ................................................................................. 6–4
6.2.3.1 Doubly Mapped Space ............................................................................ 6–4
6.2.4 Dcaches Enable/Disable and Reset .............................................................. 6–4
6.2.4.1 Enabling the Dcaches.............................................................................. 6–5
6.2.4.2 Disabling the Dcaches............................................................................. 6–5
6.3 Write Buffer (WB) .............................................................................................. 6–5
6.3.1 Bufferable Bit ................................................................................................. 6–5
6.3.2 Write Buffer Operation ................................................................................... 6–5
6.3.2.1 Writes to a Bufferable and Cacheable Location (B=1,C=1)..................... 6–5
6.3.2.2 Writes to a Bufferable and Noncacheable Location (B=1,C=0)............... 6–6
6.3.2.3 Unbufferable Writes (B=0)....................................................................... 6–6
6.3.3 Enabling the Write Buffer............................................................................... 6–6
6.3.3.1 Disabling the Write Buffer........................................................................ 6–6
6.4 Read Buffer (RB)............................................................................................... 6–6
7
Memory Management Unit (MMU) .............................................................................. 7–1
7.1 Overview ........................................................................................................... 7–1
7.1.1 MMU Registers .............................................................................................. 7–1
7.2 MMU Faults and CPU Aborts............................................................................ 7–1
7.3 Data Aborts ....................................................................................................... 7–1
7.3.1 Cacheable Reads (Linefetches) .................................................................... 7–2
7.3.2 Buffered Writes .............................................................................................. 7–2
7.4 Interaction of the MMU, Icache, Dcache, and Write Buffer ............................... 7–2
7.5 Mini Data Cache................................................................................................ 7–3
8
Clocks ........................................................................................................................... 8–1
8.1 Intel® StrongARM SA-1110 Crystal Oscillators ................................................ 8–2
8.2 Core Clock Configuration Register.................................................................... 8–2
8.2.1 Restrictions on Changing the Core Clock Configuration ............................... 8–3
8.3 Driving Intel® StrongARM SA-1110 Crystal Pins from an External Source ...... 8–3
8.4 Clocking During Test......................................................................................... 8–4
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SA-1110 Developer’s Manual