SA1110 Datasheet, PDF (254/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Peripheral Control Module
11.8.10
UDC Endpoint 0 Data Register
The UDC endpoint 0 data register is actually an 8-bit x 8-entry bidirectional FIFO. When the host
transmits data to the UDC endpoint 0, the CPU reads the UDC endpoint 0 register to access the
data.
When the UDC is sending data to the host, the CPU writes the data to be sent into the UDC
endpoint 0 register. Although the same FIFO can be read and written by the CPU during various
points in a control sequence, the CPU may not read and write the FIFO at the same time. The
direction that the FIFO is flowing is controlled by the UDC. Normally, the UDC will be in an idle
state, waiting for the host to send commands.
When this happens, the UDC fills the FIFO with the command from the host and the CPU reads the
command from the FIFO once it has arrived. The UDC will do a partial decode of the command to
determine if the CPU is going to be filling the FIFO with data to send to the host. If so, the
direction is turned around to accept data from the CPU and have the UDC transmit the data. If the
command is such that no data will be required from the UDC, then this will not happen.
The only time the CPU may write the endpoint 0 FIFO is when a valid command from the host has
been received which requires a transmission in response, that is, a GET_DESCRIPTOR command.
0h 8000 001C
UDCD0
Read/Write
7
6
5
4
3
2
1
0
Bottom of Endpoint 0 FIFO
Reset
0
0
0
0
0
0
0
0
Read Access
7
6
5
4
3
2
1
0
Top of Endpoint 0 FIFO
Reset
0
0
0
0
0
0
0
0
Write Access
Bits
Name
Description
Top/bottom of endpoint 0 FIFO data.
7..0
DATA Read – Bottom of endpoint 0 FIFO data.
Write – Top of endpoint 0 FIFO data.
11-74
SA-1110 Developer’s Manual