SA1110 Datasheet, PDF (367/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

AC Parameters
time and output hold time: Tsdis and Tsdoh will increase and decrease, respectively, from the corresponding
table values.
Table 13-4. SA-1110 AC Timing Guidelines for Asynchronous Memory Types
Pin Name
Memory Bus
D<31:0>
nPOE, nPWE, nPIOR,
nPIOW, PSKTSEL,
nPREG, nPCE<1,2>,
A<25:0>
nIOIS16
nPWAIT
nWE, nOE
nRAS/nSDCS<3:0>
nCAS/DQM<3:0>
nCS<5:0>
RDY
RD/nWR
SDCLK<2:0>
Symbol
Parameter
Min Max Unit Note
Tdfov
Memory clock fall to D<31:0> driven valid
— 10
ns
—
Tds
D<31:0> valid to memory clock rise/fall (input
setup)
3
—
ns
1
Tdh
Memory clock rise/fall to data invalid (input hold)
3
—
ns
1
2
Tmfov
Memory clock fall to output driven valid
—
— 10
ns
—
—
Tio16s
nIOIS16 valid to memory clock rise (input setup)
3
—
ns
3
Tio16h
Memory clock rise to nIOIS16 invalid (input hold)
3
—
ns
3
Twaits
nPWAIT valid to memory clock fall (input setup)
3
—
ns
—
Twaith
Memory clock fall to nPWAIT invalid (input hold)
3
—
ns
—
Tmrov
Tmrdv
Memory clock rise to output driven valid
Memory clock rise to output driven valid
—
— 10
ns
—
— 12
ns
—
Tcasd
Memory clock rise/fall to nCAS/DQM<3:0> driven
valid
—
12
ns
4
Tcsd
Memory clock rise to nCS<5:0> driven valid
— 10
ns
—
Trdys
RDY valid to memory clock rise/fall (input setup)
3
—
ns
—
Trdyh
Memory clock rise/fall to RDY invalid (input hold)
3
—
ns
—
Trdnwr
Memory clock rise/fall to RD/nWR driven valid
— 10
ns
—
Tsdclk
Memory clock rise to SDCLK<2:0> driven valid
2.8 10.8 ns
—
Notes:
1. These input pins may be sampled on either the rising or falling edge of the memory clock.
2. These signals are PCMCIA outputs and are driven by a state machine clocked by BCLK. The user defines
BCLK by programming the number of processor clocks per BCLK. Two processor clocks make one memory
clock cycle. To ensure proper operation, the user must adhere to the protocol description.
3. These signals are PCMCIA inputs and are sampled by a state machine clocked by BCLK. The user defines
BCLK by programming the number of processor clocks per BCLK. Two processor clocks make one memory
clock cycle. To ensure proper operation, the user must adhere to the protocol description.
4. These output pins may be driven on either the rising or falling edge of the memory clock.
Table 13-5. SA-1110 AC Timing Table: MCP Interface and LCD Controller
Pin Name
Symbol
Parameter
MCP (CODEC) Interface
SFRM_C
Tsfrmv
RXD_C
Trxds
Trxdh
TXD_C
Ttxdv
LCD Controller
L_LDD<7:0>
Tpclkdv
SCLK_C rise to SFRM_C driven valid
RXD_C valid to SCLK_C fall (input setup)
SCLK_C fall to RXD_C invalid (input hold)
SCLK_C rise to TXD_C valid
L_PCLK rise/fall to L_LDD<7:0> driven valid
Min Max Unit Note
— 21
ns
—
0
—
ns
—
4
—
ns
—
— 22
ns
—
— 14
ns
1
SA-1110 Developer’s Manual
13-5