SA1110 Datasheet, PDF (69/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Clocks
8.2.1
8.3
At reset, clock switching is disabled and the DCLK is driven by MCLK. Clock switching can also
be disabled by writing to CP15 register 15 with OPC_2 = 2 and CRm = 2 (see Section 5.2.14).
Clock switching is enabled by writing to CP15 register 15 with OPC_2 = 2 and CRm = 1.
Disabling clock switching only disables switching for DCLK; it does not force the DCLK to
MCLK. However, DCLK can be forced to MCLK by forcing an instruction or data cache miss after
clock switching is disabled.
Restrictions on Changing the Core Clock Configuration
When the CPU writes to the PPCR, the core clock PLL and the 48-MHz PLL are stopped for a
period of time to allow the core clock PLL to relock to the new frequency. When these PLLs are
stopped, the core clock and all clocks derived from that clock are stopped. When this happens,
certain units within the SA-1110 (the LCD controller, all serial controllers, the DMA controller,
and the OS timer) will experience an interruption in operation for approximately 150 microseconds
after the PPCR is written.
Because of these restrictions, it is recommended that the user not change the PPCR except
immediately following a hard reset or immediately following wake-up from sleep mode. The LCD
controller, all serial controllers (except the UDC), the DMA controller, and the OS timer are
already disabled and are not affected by an interruption in their clock stream. In addition to these
restrictions, the PPCR must be written prior to enabling clock switching. Note that the 32.768-kHz
clock is not affected by any change in the PPCR and units using this clock (power management,
RTC) do not see any interruption in service during the 150 microsecond period.
Driving Intel^® StrongARM SA-1110 Crystal Pins from
an External Source
In most applications, a 3.6864-MHz crystal will be connected between the PXTAL and the
PEXTAL pins. Similarly, a 32.768-kHz crystal will be connected between the TXTAL and
TEXTAL pins. In some applications, supplying these clocks from an external source may be
preferred. This is accommodated in the SA-1110 design by:
• Supplying the 32.768-kHz clock from an external source
— Only the TXTAL pin is driven. The TEXTAL pin must be left floating.
— The peak-to-peak voltage swing on TXTAL must be at least 0.6 V and the voltage on the
pin must remain within the range of 0 V to 1 V, independent of the other power supply
voltages applied to the processor.
• Supplying a 3.6864-MHz clock from an external source
— Both PXTAL and PEXTAL are driven with complementary signals.
— The peak-to-peak voltage swing on PXTAL and PEXTAL must be at least 0.6 V and the
voltage on the pin must remain in the range of 0 V to 1 V, independent of the other power
supply voltages applied to the processor.^†
— When an external clock is being used, the pull-down path in the internal 3.6864 MHz
oscillator is active. In order to limit the current into the internal oscillator, it is
recommended that the minimum impedance to the positive supply be controlled. The
maximum current sourced by the external clock source when the clock is at its maximum
positive voltage should be about 1 mA.^†
SA-1110 Developer’s Manual
8-3