SA1110 Datasheet, PDF (272/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Peripheral Control Module
11.10.2.11 CPU and DMA Register Access Sizes
Bit positioning, byte ordering, and addressing of the HSSP is described in terms of little endian
ordering. All ICP (HSSP and UART) registers are 8 bits wide and are located in the least
significant byte of individual words. The ARM peripheral bus does not support byte or half-word
operations. All reads and writes of the ICP by the CPU should be word–wide.
Two separate, dedicated DMA requests exist for both the transmit and the receive FIFOs. If the
DMA controller is used to service the transmit and/or receive FIFOs, the user must ensure the
DMA is properly configured to perform byte–wide accesses, using 8 bytes per burst for the HSSP
and 4 bytes per burst for the UART. See later sections in this chapter for summaries of the ICP’s
UART registers and HSSP registers.
11.10.3
UART Register Definition
The ICP’s UART is the same as serial port 3’s UART except that one additional register exists to
control HP-SIR^* modulation for low-speed operation. See Section 11.11, “Serial Port 3 – UART”
on page 11-109 for a description of the programming and operation of all other features of the
ICP’s UART. Note that the user must ensure that the UART is programmed to yield the frame
format shown in Figure 11-24.
11.10.4 UART Control Register 4
UART control register 4 (UTCR4) contains two different bit fields that control various functions
for 115.2-Kbps (low-speed) IrDA transmission.
11.10.4.1
HP-SIR^* Enable (HSE)
The HP-SIR^* enable (HSE) bit controls whether the HP-SIR^* bit modulation logic is enabled or
disabled. When HSE=0, HP-SIR^* modulation is disabled, and if UART operation is enabled
(ITR=0), it is used for normal serial transmission (NRZ encoding only) rather than IrDA
communication. When HSE=1, HP-SIR^* modulation is enabled for low-speed IrDA
communication; zeros are represented by pulses that are 3/16 of the programmed bit width, while
ones are represented by no pulses.
11.10.4.2
Low-Power Mode (LPM)
The low-power mode (LPM) bit controls whether the HP-SIR^* bit modulation logic represents
zeros using a pulse that is 3/16 of the chosen bit width or a fixed 1.6 µs pulse width. When LPM=0,
zeros are encoded as a pulse, which is 3/16 of the bit width programmed within the UART’s baud
rate divisor (BRD) bit field. When LPM=1, the UART’s programmed bit length is ignored and
zeros are represented by pulses that are 1.6 µs in duration. Programming LPM=1 minimizes the
time that the off-chip LED transceiver is turned on to the minimum pulse width specified by the
IrDA low-speed standard, which in turn, minimizes power consumption.
Note: A question mark (?) signifies that the Reset value of that bit is undefined when the processor has
completed its reset cycle.
11-92
SA-1110 Developer’s Manual