SA1110 Datasheet, PDF (287/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Peripheral Control Module
The following table shows the location of the flags within HSSP status register 1. The bits within
this register are read-only and do not produce interrupt requests. Note that writes to bit 7 are
ignored and reads return zero.
0h 8004 0078
7
Reserved
6
ROR
Reset
0
0
5
CRE
0
HSSR1
4
3
EOF
TNF
0
1
2
RNE
0
Read-Only
1
TBY
0
0
RSY
0
Bits
Name
Description
Receiver synchronized flag (read-only).
0
RSY
0 – Receiver is in hunt more or is disabled.
1 – Receiver logic is synchronized with the incoming data (no interrupt generated).
Transmitter busy flag (read-only).
1
TBY
0 – Transmitter is idle (continuous preambles) or disabled.
1 – Transmit logic is currently transmitting a frame (address, control, data, CRC, or
start/stop flag); no interrupt generated.
Receive FIFO not empty (read-only).
2
RNE
0 – Receive FIFO is empty.
1 – Receive FIFO is not empty (no interrupt generated).
Transmit FIFO not full (read-only).
3
TNF
0 – Transmit FIFO is full.
1 – Transmit FIFO is not full (no interrupt generated).
End of frame (read-only).
4
EOF
0 – Current frame has not completed.
1 – The value at the bottom of the receive FIFO is the last byte of data within the frame.
CRC error (read-only).
5
CRE
0 – No CRC check errors encountered in the receipt of data.
1 – CRC calculated on the incoming data. Does not match CRC value contained within the
received frame.
Receive FIFO overrun (read-only).
6
ROR
0 – Receive FIFO has not experienced an overrun.
1 – Receive logic attempted to place data into receive FIFO while it was full; the next data
value in the FIFO is the last piece of “good” data before the FIFO was overrun.
7
—
Reserved.
SA-1110 Developer’s Manual
11-107