SA1110 Datasheet, PDF (250/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Peripheral Control Module
11.8.8 UDC Endpoint 1 Control/Status Register
The UDC endpoint 1 control/status register contains 6 bits that are used to operate endpoint 1
(OUT endpoint). The table below defines the UDC Endpoint 1 Control/Status Register.
Note: Bits 7..6 are reserved for future use.
Reset
0h 8000 0014
7
6
Reserved
0
0
5
RNE
0
UDCCS1
4
3
FST
SST
0
0
2
RPE
0
Read/Write
1
RPC
0
0
RFS
0
Bits
Name
Description
Receive FIFO service (read-only).
0
RFS
0 – Receive FIFO has less than 12 bytes.
1 – Receive FIFO has 12 bytes or more.
Receive packet complete (read/write 1 to clear).
1
RPC 0 – Error/status bits invalid.
1 – Receive packet has been received and error/status bits are valid.
Receive packet error (read-only).
2
RPE
0 – Receive packet has no errors.
1 – Receive packet has errors; valid only when RPC is set.
Sent stall (read/write 1 to clear).
3
SST
1 – STALL handshake was sent; valid only when RPC is set.
Force stall (read/write).
4
FST
1 – Issue STALL handshakes to OUT tokens.
Receive FIFO not empty (read-only).
5
RNE
0 – Receive FIFO empty.
1 – Receive FIFO not empty.
Reserved.
7..6
—
Always reads zero.
The following subsections provide detailed information on the UDC Endpoint 1 Control/Status
Register.
11.8.8.1
Receive FIFO Service (RFS)
The receive FIFO service bit will be set if the receive FIFO has between 8 and 12 or more bytes
(out of 20) in it. Because the FIFOs are asynchronous, the exact threshold cannot be determined,
but is guaranteed to be in this range. This signal is also used as a DMA request signal to trigger the
DMA unit to service the FIFO.
11-70
SA-1110 Developer’s Manual