SA1110 Datasheet, PDF (237/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Peripheral Control Module
detected by the host when an SE0 persists for more than 2.5 µs (30-bit times). When the UDC is
connected to the USB cable, the pull-up resistor on the UDC+ pin causes D+ to be pulled above the
single-ended high threshold level. After 2.5 µs elapse, the host detects a connect.
After this point, the bus is in the idle state because UDC+ is high and UDC- is low. A start of
packet is signalled by transitioning the bus from the idle to the resume state (a 1 to 0 transition).
The beginning of each USB packet begins with a sync field, which starts with the 1-to-0 transition
(see the Section 11.8.1.1, “Signalling Levels” on page 11-56). After the packet data has been
transferred, an end of packet is signalled by pulling both UDC+ and UDC- low for 2-bit times,
followed by an idle for 1-bit time. If the idle persists for more than 3 ms, the UDC enters suspend
mode and it is placed in low-power mode. The UDC can be awakened from the suspend state by
the host by switching the bus to the resume state via normal bus activity, or by signalling a reset.
Under normal operating conditions, the host ensures that devices do not enter the suspend state by
periodically signalling an end of packet (EOP).
11.8.1.2
Connecting the USB to the SA-1110
The following diagram shows how the USB device is connected to the SA-1110.
Caution: It is important to note that you never put the SA-1110 to sleep while the USB cable is connected to
the device. During sleep, the UDC registers are reset, and after sleep, the device will not respond
to its host-assigned address.
Figure 11-15. Connecting the USB to the SA-1110
Universal Serial
Bus
USB 5V
UDC+
UDC–
USB GND
Intel® StrongARM*
SA-1110 Processor
5V to 3.3V
GPIOn
1.5K
UDC+
UDC–
470K
470K
A8036-01
SA-1110 Developer’s Manual
11-57