SA1110 Datasheet, PDF (172/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Memory and PCMCIA Control Module
10.6.2 External Logic for PCMCIA Implementation
The SA-1110 requires external logic to complete the PCMCIA socket interface. Figure 10-22 and
Figure 10-23 show general solutions for a one– and two–socket configuration. GPIO or
memory-mapped external registers are used to control the PCMCIA interface’s reset, power
selection (VCC and VPP), and driver enable lines. Each figure shows the logical connections
necessary to support hot insertion capability. For dual–voltage support, level shifting buffers are
required for all SA-1110 input signals. Hot insertion capability requires that each socket be
electrically isolated from each other, and from the remainder of the memory system.
Note: If one or both of these features (hot insertion and dual–voltage) is not required, then you can
eliminate the logic related to the feature which is not required.
The pull-ups shown are included for compliance with PC Card Standard - Volume 2 - Electrical
Specification. Low-power systems should remove power from these pull-ups during sleep to avoid
unnecessary power consumption. The CD 2:1 # signals have been “OR’ed” before being provided
to the SA-1110. This signal is then routed into a GPIO pin for interrupt capability. Similarly,
RDY/BSY# is routed to a GPIO. The INPACK# signal is not used. In the data bus transceiver
control logic, nPCE1 should control the enable for the low byte lane and nPCE2 should control the
enable for the high byte lane.
10-58
SA-1110 Developer’s Manual