SA1110 Datasheet, PDF (299/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Peripheral Control Module
When UTDR is written, the topmost entry of the 8-bit transmit FIFO is accessed. After a write, data is
automatically transferred down to the lowest location within the transmit FIFO that does not already
contain valid data. Data is removed from the bottom of the FIFO one piece at a time by the transmit
logic and is loaded into the transmit serial shifter along with start and stop bits (and the optional parity
and second stop bits), then is serially shifted out onto the TXD3 pin at the programmed baud rate.
Note:
There may be a delay between the writing of data in the transit FIFO and the assertion of TBY in
UTSR1. When the TBY status bit is set, there is some propagation delay for data moving through
the FIFO and getting to the serial shifter. The programmer should either use the interrupt
functionality of the UART module or wait for a 0 to 1 transition and then a 1 to 0 transition of TBY
to ensure that the data is transmitted.
The following table shows the bit locations corresponding to the data field, parity, framing, and
receiver overrun error bits within the UART data register. Note that both FIFOs are cleared when
the SA-1110 is reset, the transmit FIFO is cleared when writing TXE=0, and the receive FIFO is
cleared when writing RXE=0.
0h 8005 0014
UTDR
Read/Write
10
9
8
7
6
5
4
3
2
1
0
ROR FRE
PRE
Bottom of Receive FIFO Data
Reset 0
0
0
0
0
0
0
0
0
0
0
Read Access
Note: ROR, FRE, PRE are not read, but rather are transferred to corresponding status bits in UTSR1 each time a
data value is transferred to UTDR.
7
6
5
4
3
2
1
0
Top of Transmit FIFO Data
Reset
0
0
0
0
0
0
0
0
Write Access
Bits
Name
Description
Top/bottom of transmit/receive FIFO data.
7..0
DATA _{Read – Bottom of receive FIFO data.}
Write – Top of transmit FIFO data.
Parity error.
0 – No parity errors encountered in the receipt of this data (or parity disabled).
8
PRE
1 – Parity error encountered in the receipt of this data.
Note: Each time an 11-bit value reaches the bottom of the receive FIFO, bit 8 from the last
FIFO entry is transferred to the PRE bit in UTSR1.
Framing error.
0 – Stop bit for this frame was a one.
9
FRE
1 – Stop bit for this frame was a zero.
Note: Each time an 11-bit value reaches the bottom of the receive FIFO, bit 9 from the last
FIFO entry is transferred to the FRE bit in UTSR1.
Receiver overrun.
0 – No receiver overrun has been detected.
10
ROR
1 – Receive logic attempted to place data into receive FIFO while it was full; one or more
data values following this entry were lost.
Note: Each time an 11-bit value reaches the bottom of the receive FIFO, bit 10 from the
last FIFO entry is transferred to the ROR bit in UTSR1.
SA-1110 Developer’s Manual
11-119