SA1110 Datasheet, PDF (258/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Peripheral Control Module
11.8.14 UDC Register Locations
Table 11-13 shows the registers associated with the UDC and the physical addresses used to access them.
Table 11-13. UDC Control, Data, and Status Register Locations
Address
0h8000 0000
0h8000 0004
0h8000 0008
0h8000 000C
0h8000 0010
0h8000 0014
0h8000 0018
0h8000 001c
0h8000 0020
0h8000 0024
0h8000 0028
0h8000 002c
0h8000 0030
Name
UDCCR
UDCAR
UDCOMP
UDCIMP
UDCCS0
UDCCS1
UDCCS2
UDCD0
UDCWC
—
UDCDR
—
UDCSR
Description
UDC control register
UDC address register
UDC OUT max packet register
UDC IN max packet register
UDC endpoint 0 control/status register
UDC endpoint 1 (OUT) control/status register
UDC endpoint 2 (IN) control/status register
UDC endpoint 0 data register
UDC endpoint 0 write count register
Reserved
UDC transmit/receive data register (FIFOs)
Reserved
UDC status/interrupt register
11.9
Serial Port 1 – GPCLK/UART
Serial port 1 is a combination general-purpose clock controller (GPCLK) and universal
asynchronous receiver/transmitter (UART) serial controller. The user can configure it to perform
one of the two functions, but operation of both modes using serial port 1’s pins cannot occur
simultaneously However, the peripheral pin control (PPC) unit can be configured to take control of
two GPIO pins and use them for UART transmission, while serial port 1’s pins are used for
GPCLK operation. See the Section 11.13, “Peripheral Pin Controller (PPC)” on page 11-167 for a
description of how the PPC is configured to allow use of both the GPCLK and UART.
Used as a GPCLK controller, serial port 1 can output a clock on GPIO pin 16 with a frequency in
the range of 900 Hz to 3.6864 MHz.
Used as a UART, serial port 1 is identical to serial port 3. It supports most of the functionality of
the 16C550 protocol including 7 and 8 bits of data (odd, even, or no parity), one start bit, either one
or two stop bits, and transmits a continuous break signal. An interrupt is generated when a
framing, parity, or receiver overrun error is present within the bottom four entries of the receive
FIFO, when the transmit FIFO is half-empty or the receive FIFO is one- to two-thirds full, when a
begin and end of break is detected on the receiver, and when the receive FIFO is partially full and
the receiver is idle for three or more frame periods. Because programming and operation of serial
port 1 as a UART is identical to serial port 3, see the Section 11.11, “Serial Port 3 – UART” on
page 11-109 for a complete description of using serial port 1 in UART mode.
11-78
SA-1110 Developer’s Manual