SA1110 Datasheet, PDF (10/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

11.8.14 UDC Register Locations ............................................................................ 11–78
11.9 Serial Port 1 – GPCLK/UART ....................................................................... 11–78
11.9.1 GPCLK Operation...................................................................................... 11–79
11.9.1.1 Simultaneous Use of the UART and GPCLK ...................................... 11–79
11.9.2 GPCLK Control Register 0 ........................................................................ 11–79
11.9.2.1 GPCLK/UART Select (SUS)................................................................ 11–79
11.9.2.2 Sample Clock Enable (SCE) ............................................................... 11–79
11.9.2.3 Sample Clock Direction (SCD) ............................................................ 11–80
11.9.3 GPCLK Control Register 1 ........................................................................ 11–81
11.9.3.1 Transmit Enable (TXE) ........................................................................ 11–81
11.9.4 GPCLK Control Registers 2 and 3............................................................. 11–82
11.9.4.1 Baud Rate Divisor (BRD)..................................................................... 11–82
11.9.5 UART Register Locations .......................................................................... 11–83
11.9.6 GPCLK Register Locations........................................................................ 11–84
11.10 Serial Port 2 – Infrared Communications Port (ICP) ..................................... 11–84
11.10.1 Low-Speed ICP Operation......................................................................... 11–85
11.10.1.1 HP-SIR* Modulation ............................................................................ 11–85
11.10.1.2 UART Frame Format ........................................................................... 11–85
11.10.2 High-Speed ICP Operation ........................................................................ 11–86
11.10.2.1 4PPM Modulation ................................................................................ 11–86
11.10.2.2 HSSP Frame Format ........................................................................... 11–87
11.10.2.3 Address Field....................................................................................... 11–88
11.10.2.4 Control Field ........................................................................................ 11–88
11.10.2.5 Data Field ............................................................................................ 11–88
11.10.2.6 CRC Field ............................................................................................ 11–88
11.10.2.7 Baud Rate Generation......................................................................... 11–89
11.10.2.8 Receive Operation............................................................................... 11–89
11.10.2.9 Transmit Operation.............................................................................. 11–90
11.10.2.10Transmit and Receive FIFOs.............................................................. 11–91
11.10.2.11CPU and DMA Register Access Sizes ............................................... 11–92
11.10.3 UART Register Definition .......................................................................... 11–92
11.10.4 UART Control Register 4........................................................................... 11–92
11.10.4.1 HP-SIR* Enable (HSE) ........................................................................ 11–92
11.10.4.2 Low-Power Mode (LPM)...................................................................... 11–92
11.10.5 HSSP Register Definitions......................................................................... 11–93
11.10.6 HSSP Control Register 0........................................................................... 11–93
11.10.6.1 IrDA Transmission Rate (ITR) ............................................................. 11–93
11.10.6.2 Loopback Mode (LBM) ........................................................................ 11–94
11.10.6.3 Transmit FIFO Underrun Select (TUS)................................................ 11–94
11.10.6.4 Transmit Enable (TXE) ........................................................................ 11–95
11.10.6.5 Receive Enable (RXE)......................................................................... 11–95
11.10.6.6 Receive FIFO Interrupt Enable (RIE) .................................................. 11–95
11.10.6.7 Transmit FIFO Interrupt Enable (TIE).................................................. 11–96
11.10.6.8 Address Match Enable (AME) ............................................................. 11–96
11.10.7 HSSP Control Register 1........................................................................... 11–97
11.10.7.1 Address Match Value (AMV) ............................................................... 11–97
11.10.8 HSSP Control Register 2........................................................................... 11–98
11.10.8.1 Transmit Pin Polarity Select (TXP) ...................................................... 11–98
11.10.8.2 Receive Pin Polarity Select (RXP)....................................................... 11–99
11.10.9 HSSP Data Register ................................................................................ 11–100
11.10.10HSSP Status Register 0 ......................................................................... 11–102
11.10.10.1End/Error in FIFO Status (EIF) (read-only, nonmaskable interrupt) . 11–102
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SA-1110 Developer’s Manual