SA1110 Datasheet, PDF (122/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Memory and PCMCIA Control Module
Table 10-1.
SA-1110 Transactions
Bus Operation
Read single
Read burst
Burst
Size
(Words)
1
4
Read burst
8
Write single
1
Write burst
2
Write burst
3
Write burst
4
Write burst
8
Starting
Address
Bits 4:2
Any
0
4
0
Any
0, 1, 2
4, 5, 6
0, 1
4, 5
0
4
0
Description
Generated by core, DMA, or read buffer request.
Generated by read buffer or DMA request.
Generated by cacheline fills or read buffer request.
1..4 bytes are written as specified by the byte mask.
Generated by write buffer or DMA request.
All 4 bytes of each word are written. Generated by
write buffer or DMA request.
All 4 bytes of each word are written. Generated by
write buffer or DMA request.
All 4 bytes of each word are written. Generated by
write buffer or DMA request.
Cacheline copyback. All 32 bytes are written.
Generated by write buffer.
10.1.6
Read-Lock-Write
The read-lock-write sequence is generated by an SWP instruction to a noncacheable/nonbufferable
location. Locked access to memory is ensured through internal arbitration of accesses to the
memory controller. On the external memory bus it appears as a single read followed by a single
write.
10.1.7
Aborts and Nonexistent Memory
Reads from reserved address locations (as specified in the memory map) will result in a data abort
exception. Writes to reserved address space will have no effect.
Reads and writes from or to nonexistent memory are not detected in hardware. In case no memory
is selected on a read, the value last driven on the data bus is returned.
A single access to a disabled DRAM bank (MDCNFG:DEx=0) will cause a CBR refresh cycle to
all banks. This technique is used in the hardware and sleep reset procedures (see Section 10.7.1)
and the software and watchdog reset procedures (see Section 10.7.1). Zeros are returned to the
register file on reads and writes are dropped. A burst read access to a disabled DRAM bank will
result in a data abort exception.
10-8
SA-1110 Developer’s Manual