SA1110 Datasheet, PDF (87/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

System Control Module
9.2.1.5
Interrupt Controller Control Register (ICCR)
The interrupt controller control register (ICCR) contains a single control bit, the disable idle mask
bit (DIM). When set, this bit inhibits the idle mode operation where the output of the ICMR is
OR’ed to all ones. If this bit is set, then the interrupts that are capable of bringing the SA-1110 out
of idle mode are defined by the contents of the ICMR. The following table shows the location of all
interrupt level bits in the ICCR.
0h 9005 000C
ICCR
Read/Write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ? 0 0 0 0 0 0 0 0 0 0 0 0
Bits
0
31..1
Name
DIM
—
Description
Disable idle mask.
0 – All enabled interrupts will bring the SA-1110 out of idle mode.
1 – Only enabled and unmasked (as defined in the ICMR) will bring the SA-1110 out of idle
mode. This bit is cleared during all resets.
Reserved
SA-1110 Developer’s Manual
9-17