SA1110 Datasheet, PDF (164/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Memory and PCMCIA Control Module
Figure 10-17. Variable Latency I/O Write Timing (Burst-of-Four, with One Wait Cycle Per Beat)
CPU
Clock
Memory
Clock
nCS4
A(25:0)
nWE
nOE
t_AS
t_CES
t_ASRW0
A0
t_AH
t_ASRWN
A0+4
RDN+1
RDF+1+WAITS
RD/nWR
RDY
t_DSWH
D(31:0)
D0
t_DH
D1
nCAS[3:0]
A0+8
D2
t_CEH
max(2*RRR,1)
A0+12
D3
A6655-02
In Figure 10-16 and Figure 10-17, some of the parameters are defined as follows:
tAS = Address setup to nCS = 1 CPU cycle
tCES = nCS, nCAS/DQM setup to nOE or nWE = 2 memory clock cycles (4 CPU cycles)
tASRW0 = Address setup to nOE or nWE low (asserted) = 2.5 memory cycles on first beat
tASRWN = Address setup to nOE or nWE low (asserted) = (RDN+0.5) memory cycles on
subsequent beats
tDSWH,min = Minimum Write data setup to nWE high (deasserted) = (RDF+1.5) memory cycles
tDH = Data hold after nWE high (deasserted) = 1/2 memory cycle (1 CPU cycle)
tCEH = nCS, nCAS/DQM held asserted after nOE or nWE deasserted = 1 memory clock cycle
tAH = Address hold after nOE or nWE deasserted = 1/2 memory cycle (1 CPU cycle)
nOE or nWE high time between burst beats = (RDN+1) memory cycle
10-50
SA-1110 Developer’s Manual