SA1110 Datasheet, PDF (133/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Memory and PCMCIA Control Module
10.2.3.2
of 2 CPU clock cycles). When MDCNFG:CDB20 is "1" or MDCNFG:DWID0 is "1", the
MDCAS00 must contain "1"s in the lower 2 bits and each transition of nCAS/DQM must be a
minimum of 1 bit.
MDCAS Registers with SDRAM and SMROM
See Table 10-3 for a description of possible MDCAS encodings for SDRAM or SMROM. nSDCAS
asserts as indicated by the first "1" to "0" transition: similar to the behavior of nCAS/DQM for
asynchronous DRAM. But, because the least significant bit of MDCAS goes out on nSDCAS one
CPU cycle after the assertion of nRAS/nSDCS, the RAS-to-CAS delay is one CPU cycle greater
than the number of leading 1’s. A RAS-to-CAS delay of N (for example 2, 3, or 4) memory cycles
corresponds to 2N-1 (for example 3, 5, or 7) leading 1’s. For SDRAM, nSDCAS remains asserted
throughout the burst, regardless of subsequent transitions programmed into MDCAS. For SMROM,
nSDCAS is asserted only through the first column address. In either case, subsequent "0" to "1"
transitions must be programmed to reference the data input latch delay (MDCNFG:TDL0,2 or
SMCNFG:CL0,2) for every beat of the burst. The first "0" to "1" transition must be either one-half
or one memory cycles (1 or 2 bits) after the first "1" to "0" transition: The latter option (2 initial "0"
bits) provides an additional CPU cycle of delay for data latching. It is ignored unless
MDREFR:KnDB2=0 (using memory clock frequency), and is useful under the following common
circumstances (evaluated for specific load):
max(mem clock to SDCLK delay) + max(SDCLK to data delay) + max(data to mem clock set up) >= Tmem
max(mem clock to SDCLK delay) + max(SDCLK to data delay) + max(data to mem clock set up) <= Tmem + Tcpu
min(mem clock to SDCLK delay) + min(SDCLK to data delay) + min(data to mem clock set up) >= Tcpu
Note: Subsequent to the first "0" to "1" transition, MDCAS must be filled through the 96th bit with the
2-bit repeating pattern of "0" followed by "1".
Chapter 13, “AC Parameters” provides frequency-dependent guidelines for using the delayed
latching option.
Sharing MDCAS Registers
Asynchronous DRAM or SDRAM can share MDCAS registers with SMROM. Asynchronous
DRAM must use CDB2n=1 and/or the CPU clock period (labeled "Tcpu" in Table 10-3) must be
fairly large. SDRAM and SMROM can share MDCAS registers if they use the same RAS-to-CAS
delay (the entries labeled “trcd” in Table 10-3). If both the SDRAM and SMROM use the memory
clock frequency, they must also use the same clock edge for read data latching.
MDCAS registers can be shared even if the SDRAM and SMROM are running at different
frequencies (For example, SMROM using SDCLK 0 with MDREFR:K0DB2=1 and SDRAM using
SDCLK 1 with MDREFR:K1DB2=0). This is possible because the minimum number of clock
cycles for RAS-to-CAS delay typically scales with frequency.
Reference edges for CAS latency are made insensitive to the clock divisor by ignoring
odd-numbered (first, third, and so forth) "0" to "1" transitions if MDREFR:K0DB2=1 for SMROM,
MDREFR:K1DB2=1 for SDRAM bank pair 0/1, or MDREFR:K2DB2=1 for SDRAM bank pair
2/3). The number of “0” to “1” transitions required to serve a burst transaction becomes twice the
SA-1110 Developer’s Manual
10-19