SA1110 Datasheet, PDF (134/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Memory and PCMCIA Control Module
burst length. By repeating the pattern of “0” to “1” transitions up through the most significant bit of
MDCAS, one can ensure that an internal burst length of eight will always be accommodated: even
if the transaction uses a 16-bit data bus (SDRAM, but not SMROM) and the memory clock divisor.
Table 10-3 describes how DRAM and synchronous memories can share MDCAS registers.
Key to Table:
Tcpu – CPU clock period
trcd – RAS-to-CAS delay
tccd – CAS-to-CAS delay
tac – Delay from SDCLK rising edge to read data (D) latching edge
tcas – CAS low time
tcp – CAS high time
Table 10-3. Timing Interpretations of Possible SDRAM/SMROM MDCAS Settings
Possible SDRAM/SMROM Settings for:
MDCASn0 31:0
MDCASn1 31:0
MDCASn2 31:0
0101 0101 0101 0101 0101 0101 0101 0111
0101 0101 0101 0101 0101 0101 0101 0101
0101 0101 0101 0101 0101 0101 0101 0101
1010 1010 1010 1010 1010 1010 1010 0111
1010 1010 1010 1010 1010 1010 1010 1010
1010 1010 1010 1010 1010 1010 1010 1010
0101 0101 0101 0101 0101 0101 0101 1111
0101 0101 0101 0101 0101 0101 0101 0101
0101 0101 0101 0101 0101 0101 0101 0101
1010 1010 1010 1010 1010 1010 1001 1111
1010 1010 1010 1010 1010 1010 1010 1010
1010 1010 1010 1010 1010 1010 1010 1010
0101 0101 0101 0101 0101 0101 0111 1111
0101 0101 0101 0101 0101 0101 0101 0101
0101 0101 0101 0101 0101 0101 0101 0101
1010 1010 1010 1010 1010 1010 0111 1111
1010 1010 1010 1010 1010 1010 1010 1010
1010 1010 1010 1010 1010 1010 1010 1010
SDRAM/SMROM
Timing Interpretation
KnDB2 = 0
trcd=4*Tcpu
tccd=2*Tcpu
tac=2*Tcpu
KnDB2 = 1
trcd=4*Tcpu
tccd=4*Tcpu
tac=4*Tcpu
trcd=4*Tcpu
tccd=2*Tcpu
tac=3*Tcpu
trcd=6*Tcpu
tccd=2*Tcpu
tac=2*Tcpu
trcd=4*Tcpu
tccd=4*Tcpu
tac=4*Tcpu
Not Applicable
trcd=6*Tcpu
tccd=2*Tcpu
tac=3*Tcpu
trcd=8*Tcpu
tccd=2*Tcpu
tac=2*Tcpu
Not Applicable
trcd=8*Tcpu
tccd=4*Tcpu
tac=4*Tcpu
trcd=8*Tcpu
tccd=2*Tcpu
tac=3*Tcpu
trcd=8*Tcpu
tccd=4*Tcpu
tac=4*Tcpu
Asynchronous DRAM
Timing Interpretation
CDB2n = 0
trcd=3*Tcpu
tcas=1*Tcpu
tcp=1*Tcpu
CDB2n = 1
trcd=6*Tcpu
tcas=2*Tcpu
tcp=2*Tcpu
trcd=3*Tcpu
tcas=1*Tcpu
tcp=1*Tcpu
trcd=5*Tcpu
tcas=1*Tcpu
tcp=1*Tcpu
trcd=6*Tcpu
tcas=2*Tcpu
tcp=2*Tcpu
trcd=10*Tcpu
tcas=2*Tcpu
tcp=2*Tcpu
trcd=5*Tcpu
tcas=1*Tcpu
tcp=1*Tcpu
trcd=7*Tcpu
tcas=1*Tcpu
tcp=1*Tcpu
trcd=10*Tcpu
tcas=2*Tcpu
tcp=2*Tcpu
trcd=14*Tcpu
tcas=2*Tcpu
tcp=2*Tcpu
trcd=7*Tcpu
tcas=1*Tcpu
tcp=1*Tcpu
trcd=14*Tcpu
tcas=2*Tcpu
tcp=2*Tcpu
10.2.4
Static Memory Control Registers (MSC2 – 0)
MSC2, MSC1, and MSC0 are read/write registers and contain control bits for configuring static
memory (or variable latency I/O) that correspond to chip select pairs nCS(5:4), nCS(3:2), and
nCS(1:0), respectively. Timing fields are specified as numbers of memory clock cycles. The
memory clock cycle consists of two CPU cycles. Each of the three registers contains two identical
CNFG fields: one for each chip select within the pair. Please note the distinct descriptions for
nCS(5:3) variable latency I/O in the following table.
On hardware or sleep reset, the MSC0: 15:0 field is set to 0b 1111 1111 1111 1x00 (binary) where x
represents the inverse of the ROM_SEL pin. This forces nCS(0) to the slowest possible nonburst
ROM timings. All other fields in MSC0, MSC1, and MSC2 are unaffected by reset; question marks
indicate that the values are unknown at hardware or sleep reset.
10-20
SA-1110 Developer’s Manual