SA1110 Datasheet, PDF (190/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Peripheral Control Module
11.6.1.2
DMA Control/Status Register (DCSRn)
The DCSRn is a 32-bit read/write register that contains control and status bits for the channel. The
following figure shows the format for this register; question marks indicate that the values are
unknown at reset.
DCSRn
Read/Write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ?0 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
Bits
0
1
2
3
4
5
6
7
31..8
Name
RUN
IE
ERROR
DONEA
STRTA
DONEB
STRTB
BIU
—
Description
Run bit.
This is a control bit and is set by the user to indicate that the device address register has
been loaded. No transfer will occur on this channel unless this bit is set. Clearing the RUN
bit on an active channel acts as a pause to that channel. Operation can then be resumed
by again setting the RUN bit.
Interrupt enable.
This bit enables interrupts to be passed onto the interrupt controller. An interrupt is the “OR”
of the DONEA, DONEB, and ERROR bits.
Transfer error bit.
ERROR is a status bit and is set to indicate that a memory error has occurred. It can generate
an interrupt if the IE bit is set. ERROR is cleared by software through setting the RUN bit.
Buffer A done.
This bit is a status bit and indicates that the transfer into or out of buffer A has completed. It
is cleared by writing a one to it or by setting the STRTA bit. DONEA can generate an
interrupt if IE is set.
Buffer A transfer start.
This bit is a control bit and is written by the user. It causes the buffer A transfer to begin.
This bit is functional only if the RUN bit is set.
This bit is a status bit and indicates that the transfer into or out of buffer B has completed. It
is cleared by writing a one to it or by setting the STRTB bit. DONEB can generate an
interrupt if IE is set.
Buffer B transfer start.
This bit is a control bit and is written by the processor. It causes the buffer B transfer to
begin. This bit is functional only if the RUN bit is set.
Buffer in use.
BIU is a status bit and may be read to indicate which buffer (A or B) is active . This bit is
toggled by the DMA controller when DONEA or DONEB are set. This bit is cleared by all
reset sources (hard, sleep, watchdog, or software).
Reserved.
These bits are reserved and read as zeros. Writes to this field have no effect.
11-10
SA-1110 Developer’s Manual