SA1110 Datasheet, PDF (249/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Peripheral Control Module
11.8.7.5
Data End (DE)
The data end bit is set by the UDC after it writes the last packet for the current descriptor. Once the
current setup transfer has ended, the UDC clears this bit. When this bit is cleared the EIR bit in the
UDC status/interrupt register will be set if endpoint zero interrupts are enabled. If there is no data
phase, the CPU should set this bit at the same time it clears the OPR bit (0).
11.8.7.6
Setup End (SE)
The setup end bit is set by the UDC when a control transfer ends before the DE bit (4) gets set.
When this bit is set the EIR bit in the UDC status/interrupt register will be set if endpoint zero
interrupts are enabled. This bit is cleared by writing a one to the serviced setup end bit (7). When
the CPU detects this bit being set (if the OPR bit (0) is also set), then it should unload the new setup
packet after it clears setup end.
11.8.7.7
Serviced OPR (SO)
The serviced bit will clear the OPR bit (0) when writing a one.
11.8.7.8 Serviced Setup End (SSE)
The serviced setup end bit will clear the SE bit (5) when writing a one.
0h 8000 0010
UDCCS0
Read/Write
7
6
5
4
3
2
1
0
SSE
SO
SE
DE
FST
SST
IPR
OPR
Reset
0
0
0
0
0
0
0
0
Bits
Name
Description
OUT packet ready (read-only).
0
OPR
1 – OUT packet ready.
IN packet ready (read/write 1 to set).
1
IPR
1 – IN packet ready.
Sent stall (read/write 1 to clear).
2
SST
1 – UDC sent stall handshake.
Force stall (read/write 1 to set).
3
FST
1 – Force stall handshake.
Data end (read/write 1 to set).
4
DE
1 – The last byte of the data phase has been written.
Setup end (read-only).
5
SE
1 – Control transfer ended before data end got set.
Serviced OPR (write-only).
6
SO
1 – Clear OPR, bit 0.
Serviced setup end (write-only).
7
SSE
1 – Clear SE, bit 5.
SA-1110 Developer’s Manual
11-69