SA1110 Datasheet, PDF (48/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Coprocessors
Register 1 – Control
Read/Write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Undefined
XI
R S B 1 1 1 WC AM
Bits
13
31..14
Name
X
—
(Sheet 2 of 2)
Description
Virtual interrupt vector adjust
0 – Base address of interrupt vectors is 0h0000 0000
1 – Base address of interrupt vectors is 0hFFFF 0000
Unused.
Undefined on Read. Writes ignored.
5.2.3
Register 2 – Translation Table Base
Register 2 is a read/write register that holds the base of the currently active level 1 page table. Bits
13:0 are undefined on read, ignored on write.
Register 2 – Translation Table
Base
Read/Write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Translation Table Base
Undefined
5.2.4
Register 3 – Domain Access Control
Register 3 is a read/write register that holds the current access control for domains 0 to 15. Refer to
the ARM Architecture Reference for a description of the domain structure.
Register 3 – Domain Access
Control
Read/Write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
5-4
SA-1110 Developer’s Manual