SA1110 Datasheet, PDF (320/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Peripheral Control Module
0h 8006 0000
MCP Control Register 0: MCCR0
Read/Write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
ECP
TSD
ASD
Reset 0 0 0 0 0 0 0 0 ? ? ? ? ? ? ? 0 0 ? ? ? ? ? ? ? 0 ? ? ? ? ? ? ?
(Sheet 3 of 3)
Bits
25..24
31..26
Name
ECP
—
Description
External clock prescaler.
00 – Clock input using GPIO pin 21 is divided by one before being used to drive the frame
rate.
01 – Clock input using GPIO pin 21 is divided by two before being used to drive the frame rate.
10 – Clock input using GPIO pin 21 is divided by three before being used to drive the frame
rate.
11– Clock input using GPIO pin 21 is divided by four before being used to drive the frame rate.
Note: ECP is used only when ECS=1. Also, the maximum clock frequency allowed to drive
the frame rate after ECS has divided down the input clock is 12 MHz.
Reserved.
11.12.4 MCP Control Register 1
The MCP control register 1 (MCCR1) contains one bit that selects one of two fixed frequencies to
drive the MCP. Note that this register resides within the PPC’s address space.
11.12.4.1 Clock Frequency Select (CFS)
When the on-chip clock is enabled (ECS=0), the clock frequency select (CFS) bit is used to select
either a 9.585-MHz or an 11.981-MHz clock to drive the MCP’s serial clock rate. When ECS=0
and CFS=0, the on-chip 3.6864-MHz oscillator is first multiplied by 13 then divided by 4, resulting
in an 11.9808-MHz bit clock frequency. When ECS=0 and CFS=1, the on-chip 3.6864 MHz
oscillator is first multiplied by 13 then divided by 5, resulting in a 9.58464-MHz bit clock
frequency. Note that when ECS=1, CFS is ignored and an external clock is input to the MCP via
GPIO pin 21. Also note that CFS is cleared following a reset of the SA-1110 so that the MCP
defaults to 11.981-MHz operation, which is standard for the UCB1100/1200.
The following table shows the location of the CFS control bit within the MCP control register 1.
The CFS is cleared to zero selecting 11.981-MHz operation following a reset of the SA-1110.
Writes to reserved bits are ignored and reads return zeros. MCCR1 resides within the PPC’s
address space.
11-140
SA-1110 Developer’s Manual