SA1110 Datasheet, PDF (180/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Memory and PCMCIA Control Module
— Alternate master deasserts MBREQ
— SA-1110 deasserts SDCKE 1 at time (t)
— SA-1110 deasserts MBGNT at time (t + 1*Tmem)
— Alternate master tristates DRAM outputs prior to time (t + 2*Tmem)
— SA-1110 begins to drive DRAM outputs at time (t + 3*Tmem)
— SA-1110 asserts SDCKE 1 at time (t + 4*Tmem)
If the refresh counter inside the SA-1110 requested a refresh cycle during the alternate master
tenure, then that refresh cycle is run first, followed by any other bus transactions that stalled during
that period. This mode is set up by writing registers as follows:
• Write the GPIO pin direction register (GPDR) at physical address 0x9004 0004 so as to set bit
21 (make GPIO 21 an output) and clear bit 22 (make GPIO 22 an input).
• Write the GPIO alternate function register (GAFR) at physical address 0x9004 001C so as to
set bits 21 (enable the MBGNT alternate output function) and 22 (enable the MBREQ
alternate input function).
• Write the test unit control register (TUCR) at physical address 0x9003 0008 so as to set bit 10
(enable the memory request mode).
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SA-1110 Developer’s Manual