SA1110 Datasheet, PDF (100/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

System Control Module
• In the second step of the wake-up sequence (after the power ramp timer has expired), the
following actions occur:
a. A second internal timer begins to time the 3.686-MHz oscillator as it begins to ramp up to
speed. This timer waits for 150 ms. If the OPDE bit in the PCFR is zero, then the
oscillator was never disabled and this timer is not used. In this case, the power manager
transitions to the third step directly without waiting for the oscillator timer to complete.
b. If BATT_FAULT or VDD_FAULT is asserted at any time during the oscillator ramp, the
power manager transitions back to sleep mode through the fault state.
• In the third step of the wake-up sequence (after the 3.6864-MHz oscillator is stabilized), the
following actions occur:
a. The SA-1110 internal reset is negated and the CPU begins a normal boot sequence.
b. The RESET_OUT pin is negated, indicating that the SA-1110 is about to perform a fetch
from the reset vector location.
During the fault state entered through the assertion of VDD_FAULT or BATT_FAULT, the
following actions occur:
• All potential wake-up sources are cleared (all GPIO edge detects and the RTC alarm interrupt).
• The power manager wake-up source register (PWER) is loaded with 0x0000 0003 and bits 0
and 1 of the GFER and the GRER (see the Section 9.1, “General-Purpose I/O” on page 9-1)
are set. This limits the potential wake-up sources to a rising or falling edge on GP 0 or GP 1.
This wake-up fault state is provided to prevent spurious events from causing an unwanted
wake-up during a low battery or shorted power supply situation. This fault state setting of
PWSR, GRER, and GFER registers is also the default state of the registers after a hardware
reset.
9.5.3.6 Booting After Sleep Mode
When the SA-1110 boots after sleep mode (or at any other time), it must examine the reset
controller status register (RCSR) to determine why it just booted. This register has bits to indicate
sleep reset, software reset, watchdog reset, or hardware reset (assertion of nRESET). See
Section 9.6, “Reset Controller” on page 9-42 for more details on reset.
Next, software should examine the power manager sleep status register (PSSR) to determine why it
was in sleep. This register has bits to indicate whether a VDD_FAULT, BATT_FAULT, or force
sleep bit has been asserted since the register was last cleared. It is possible for multiple bits to be set
in this register.
Also, the SA-1110 provides the power manager scratch pad register (PSPR) for saving any general
processor state during sleep. This register may be written by the processor and the contents will
survive sleep mode. The bits in this register are not explicitly used by the SA-1110, but may be
used by software to index into ROM space to retrieve memory controller configuration, for
example.
Note: The nRESET pin must not be asserted during sleep mode if the DRAM contents are to be
preserved. The assertion and subsequent negation of nRESET during sleep mode causes the
SA-1110 to clear the FS bit in the force sleep register, assert PWR_EN, time the PLL lock
9-30
SA-1110 Developer’s Manual