SA1110 Datasheet, PDF (257/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Peripheral Control Module
11.8.13.3 Transmit Interrupt Request (TIR)
The transmit interrupt request bit gets set if the TIM bit in the UDC Control Register is cleared and
the TPC bit in the UDC endpoint 2 control/status register gets set. The TIR bit is cleared by writing
a one to it.
11.8.13.4 Suspend Interrupt Request (SUSIR)
The suspend interrupt request bit will be set if the SUSM bit in the UDC Control Register is cleared
and the USB bus remains idle for more than 3 ms. The SUSM bit gets cleared by writing a one to it.
11.8.13.5 Resume Interrupt Request (RESIR)
The resume interrupt request bit will be set if the RESM bit in the UDC Control Register is cleared,
the UDC is currently in the suspended state, and the USB bus is driven with resume signalling.
11.8.13.6 Reset Interrupt Request (RSTIR)
The reset interrupt request register will be set if the REM bit in the UDC control register is cleared
and the host issues a reset. When the host issues a reset, the entire UDC is reset. The RSTIR bit
retains its state so software can determine that the design was reset.
Reset
0h 8000 0030
7
6
Reserved
0
0
5
RSTIR
0
UDCSR
4
RESIR
0
3
SUSIR
0
Read/Write (Clear)
2
1
0
TIR
RIR
EIR
0
0
0
Bits
Name
Description
Endpoint 0 interrupt request (read/write clear).
0
EIR
1 – Endpoint 0 needs service.
Receive interrupt request (read/write clear).
1
RIR
1 – Receive endpoint (1) needs service.
Transmit interrupt request (read/write clear).
2
TIR
1 – Transmit endpoint (2) needs service.
Suspend interrupt request (read/write clear).
3
SUSIR
1 – UDC received suspend signalling from the host.
Resume interrupt request (read/write clear).
4
RESIR
1 – UDC received resume signalling from the host.
Reset interrupt request (read/write clear).
5
RSTIR
1 – UDC was reset by the host.
Reserved.
7..6
—
Always reads zero.
SA-1110 Developer’s Manual
11-77