SA1110 Datasheet, PDF (328/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Peripheral Control Module
11.12.6.11 Telecom Transmit FIFO Not Full Flag (TNF) (read-only,
noninterruptible)
The telecom transmit FIFO not full flag (TNF) is a read-only bit that is set whenever the telecom
transmit FIFO contains one or more entries that do not contain valid data and is cleared when the
FIFO is completely full. This bit can be polled when using programmed I/O to fill the telecom
transmit FIFO over its halfway mark. This bit does not request an interrupt.
11.12.6.12 Telecom Receive FIFO Not Empty Flag (TNE) (read-only,
noninterruptible)
The telecom receive FIFO not empty flag (TNE) is a read-only bit that is set whenever the telecom
receive FIFO contains one or more entries of valid data and is cleared when it no longer contains
any valid data. This bit can be polled when using programmed I/O to remove remaining bytes of
data from the receive FIFO because DMA service and CPU interrupt requests are made only when
four or more bytes reside within the FIFO (3, 2, or 1 bytes may remain at the end of a frame). This
bit does not request an interrupt.
11.12.6.13 Codec Write Completed Flag (CWC) (read-only, noninterruptible)
The codec write completed (CWC) flag is set after the following sequence occurs: a register write
command is issued to the codec by writing to MCDR2; the write command is sent to the codec via
subframe 0; the data value is latched within the addressed codec register at the beginning of
subframe 1 (the 65th bit of the frame); the address and value that was written is returned to the
MCP via the next subframe 0; and the returned values are latched in MCDR2. CWC is
automatically cleared when MCDR2 is read or written. This bit does not request an interrupt.
11.12.6.14 Codec Read Completed Flag (CRC) (read-only, noninterruptible)
The codec read completed (CRC) flag is set after the following sequence occurs: a register read
command is issued to the codec by writing to MCDR2; the read command is sent to the codec via
subframe 0; the data value contained within the addressed codec register is loaded into the codec’s
serial shift register during subframe 0 (the 41st bit of the frame); the address and value that was
read is returned to the MCP via the same subframe 0; and the returned values are latched in
MCDR2. CRC is automatically cleared when MCDR2 is read or written. This bit does not request
an interrupt.
11.12.6.15 Audio Codec Enabled Flag (ACE) (read-only, noninterruptible)
The audio codec enabled (ACE) flag indicates when the audio codec input and/or output is enabled,
which in turn, indicates that the audio sample rate counter is enabled. This flag is set after the
following sequence occurs: a register write command is issued to Audio Control Register B
(register 8), and either bit 14 or 15 is set (aud_in_ena or aud_out_ena) by writing to MCDR2; the
write command is sent to the codec via subframe 0; the data value is latched within codec register
8; and SFRM is asserted to indicate the start of the next frame. ACE is automatically cleared using
the same sequence with the exception that bits 14 and 15 are cleared, disabling both the input and
output paths of the audio codec. This bit does not request an interrupt.
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SA-1110 Developer’s Manual