SA1110 Datasheet, PDF (34/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Functional Description
2.4
Memory Map
Figure 2-3 shows the SA-1110 memory map. The map is divided into four main partitions of
1 Gbyte each.
• Physical address: 0h0000 0000 to 0h3FFF FFFF.
This partition is dedicated to static memory devices (ROM, SRAM, and Flash) and to the
PCMCIA expansion bus area. This space is divided into:
— Four 128 Mbyte blocks for static memory devices
The static memory space is intended for ROM, SRAM, and Flash memory. The bottom
partition (at 0h0000 0000) is assumed to be ROM at boot time. The SMROM_EN pin is
used to determine if the boot ROM is asynchronous or synchronous. If asynchronous,
boot ROM is selected (SMROM_EN = 0), its width (16-bit or 32-bit) is determined by the
state of the ROM_SEL pin. SMROM is supported only on 32-bit data busses.
— Two 256 Mbyte blocks for the PCMCIA interface
The PCMCIA interface is divided into Socket 0 and Socket 1 space. These partitions are
further subdivided into I/O, memory and attribute space.
• Physical address: 0h4000 0000 to 0h7FFF FFFF
This partition includes:
— Two 128 Mbyte blocks for static memory or variable latency I/O devices. This block
differs from the other three status memory spaces because it can be used for variable
latency I/O but not SRAM.
— One 768 Mbyte block of reserved space. Accessing this reserved space results in a data
abort exception.
• Physical address: 0h8000 0000 to 0hBFFF FFFF
This partition contains all on-chip registers (except those specified by the ARM V4
architecture). This block is further divided into four 256 Mbyte blocks that contain control
registers for the following major functional blocks within the processor:
— Peripheral Control Module Registers
— System Control Module Registers
— Memory and Expansion Registers
— LCD and DMA Registers
• Physical address: 0hC000 0000 to 0hFFFF FFFF
This partition contains DRAM memory and is divided into:
— Four banks of DRAM fixed at 128 Mbyte each. With multiple banks implemented, there
probably will be gaps in the map that should be mapped through the
memory-management unit.
— One 128 Mbyte block that is mapped within the memory controller and returns zeros
when read. This function is intended to facilitate rapid cache flushing by not requiring an
external memory access to load data into the cache. This space is burstable. Writes to this
space have no effect.
— One 384 Mbyte block of reserved space. Accessing this reserved space results in a data
abort exception.
2-8
SA-1110 Developer’s Manual