SA1110 Datasheet, PDF (161/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Memory and PCMCIA Control Module
Figure 10-15. SRAM Write Timing Diagram (4–Beat Burst)
Memory Clock
t_AS
nCS0
A[25:0]
nWE
RD/nWR
A0
t_CES
t_DSWH
RDN+1
D[31:0]
D0
nCAS[3:0]
t_CEH
max(2*RRR,1)
t_AH
A0+4
t_ASW
t_DH
RDN+1
A0+8
RDN+1
A0+12
RDN+1
D1
D2
D3
Contents of static memory register fields:
MSC0: RDN0=2 MSC0:RRR0=2
A6643-02
In Figure 10-15 some of the parameters are defined as follows:
tAS = Address setup to nCS = 1 CPU cycle
tCES = nCS, nCAS/DQM setup to nWE = 2 memory clock cycles (4 CPU cycles)
tASW = Address setup to nWE low (asserted) = 1/2 memory cycle (1 CPU cycle)
[For A 25:5, tASW=5 CPU cycles. For A 4:2, tASW=1 CPU cycle for subsequent beats in a burst]
tDSWH = Write data setup to nWE high (deasserted) = 1/2 memory cycle + (RDN+1) memory cycles
tDH = Data hold after nWE high (deasserted) = 1/2 memory cycle (1 CPU cycle)
tCEH = nCS, nCAS/DQM held asserted after nWE deasserted = 1 memory clock cycle (2 CPU
cycles)
tAH = Address hold after nWE deasserted = 1/2 memory cycle (1 CPU cycle)
nWE high time between burst beats = 1 memory cycle (2 CPU cycles)
SA-1110 Developer’s Manual
10-47