SA1110 Datasheet, PDF (305/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Peripheral Control Module
The following table shows the bit locations corresponding to the flag bits within UART status
register 1. Note that these flags do not generate interrupts, all bits are read-only, writes are ignored,
and reads of reserved bits return zeros.
Reset
0h 8005 0020
7
6
Reserved
0
0
5
ROR
0
UTSR1
4
FRE
?
3
PRE
?
Read-Only
2
1
0
TNF
RNE
TBY
?
0
0
Bits
Name
Description
Transmitter busy flag (read-only).
0
TBY
0 – Transmitter is idle or UART is disabled.
1 – Transmit logic is currently transmitting a frame (data within the serial shifter); no
interrupt generated.
Receive FIFO not empty (read-only).
1
RNE
0 – Receive FIFO is empty.
1 – Receive FIFO is not empty (no interrupt generated).
Transmit FIFO not full (read-only).
2
TNF
0 – Transmit FIFO is full.
1 – Transmit FIFO is not full (no interrupt generated).
Parity error (read-only).
0 – No parity errors encountered in the receipt of the next data value in the FIFO (or parity
3
PRE
disabled).
1 – Parity error encountered in the receipt of the next data value in the FIFO (no interrupt
generated).
Framing error (read-only).
4
FRE
0 – Stop bit for the next frame in the FIFO was a one.
1– Stop bit for the next frame in the FIFO was a zero (no interrupt generated).
Receive FIFO overrun (read-only).
0 – Receive FIFO has not experienced an overrun.
5
ROR
1 – Receive logic attempted to place data into receive FIFO while it was full, the next data
value in the FIFO is the last piece of “good” data before the FIFO was overrun (no interrupt
generated).
7..6
—
Reserved.
SA-1110 Developer’s Manual
11-125