SA1110 Datasheet, PDF (32/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Functional Description
Table 2-1.
Signal Descriptions (Sheet 3 of 4)
Name
SCLK_C
SFRM_C
UDC+
UDC-
TXD_1
RXD_1
TXD_2
RXD_2
TXD_3
RXD_3
GP 27:0
SMROM_EN
Type
OCZ
OCZ
ICOCZ
ICOCZ
OCZ
IC
OCZ
IC
OCZ
IC
ICOCZ
IC
ROM_SEL
IC
PXTAL
PEXTAL
TXTAL
TEXTAL
PWR_EN
IC
OCZ
IC
OCZ
OCZ
BATT_FAULT IC
VDD_FAULT IC
nRESET
IC
nRESET_OUT OCZ
nTRST
IC
Description
CODEC clock.
CODEC frame signal.
Serial port zero bidirectional, differential signalling pin (UDC).
Serial port zero bidirectional, differential signalling pin (UDC).
Serial port one transmit pin (UART).
Serial port one receive pin (UART).
Serial port two transmit pin (IrDA).
Serial port two receive pin (IrDA).
Serial port three transmit pin (UART).
Serial port three receive pin (UART).
General-purpose input output.
Synchronous mask ROM (SMROM) enable. This pin is used to determine if the
boot ROM (static memory bank 0) is asynchronous or synchronous. If
asynchronous, boot ROM is selected (SMROM_EN = 0) and its width is
determined by the state of the ROM_SEL pin. SMROM is supported only on 32-bit
data busses.
ROM select. This pin is used to configure the ROM width. It is either grounded or
pulled high. If ROM_SEL is grounded, the ROM width is 16 bits. If ROM_SEL is
pulled up, the ROM width is 32 bits.
Input connection for 3.686-MHz crystal (non-CMOS threshold).
Output connection for 3.686-MHz crystal (non-CMOS level).
Input connection for 32.768-kHz crystal (non-CMOS threshold).
Output connection for 32.768-kHz crystal (non-CMOS level).
Power enable. Active high. PWR_EN enables the external VDD power supply.
Deasserting it signals the power supply that the system is going into sleep mode
and that the VDD power supply should be removed.
Battery fault. Signals the SA-1110 that the main power source is going away
(battery is low or has been removed from the system). The assertion of
BATT_FAULT causes the SA-1110 to enter sleep mode. The SA-1110 will not
recognize a wake-up event while this signal is asserted.
VDD fault. Signals the SA-1110 that the main power supply is going out of
regulation (shorted card is inserted). VDD_FAULT will cause the SA-1110 to enter
sleep mode. VDD_FAULT is ignored after a wake-up event until the power supply
timer completes (approximately 10 ms).
Hard reset. This active low signal is a level-sensitive input used to start the
processor from a known address. A low level will cause the current instruction to
terminate abnormally, and the on-chip caches, MMU, and write buffer to be
disabled.
When nRESET is driven high, the processor will restart from address 0. nRESET
must remain low until the power supply is stable and the internal 3.686-MHz
oscillator has come up to speed. While nRESET is low, the processor will perform
idle cycles.
Reset out. This signal is asserted when nRESET is asserted and deasserts when
the processor has completed resetting. nRESET_OUT is also asserted for "soft"
reset events (sleep and watchdog).
Test interface reset. Note this pin has an internal pull-down resistor and must be
driven high to enable the JTAG circuitry. If left unconnected, this pin is pulled low
and disables JTAG operation.
2-6
SA-1110 Developer’s Manual