SA1110 Datasheet, PDF (16/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

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SDRAM 8-Beat Read/Write Timing for 4 Bank x 4 M x 4 Bit
Organization (64 Mbit)................................................................................... 10–39
DRAM/SDRAM CBR Refresh Cycle ............................................................. 10–41
Burst-of-Eight ROM or Flash Read Timing Diagram..................................... 10–43
Eight-Beat Burst Read from Burst-of-Four ROM or Flash............................. 10–44
Nonburst ROM, SRAM, or Flash Read Timing Diagram – Four Data Beats) 10–45
SRAM Write Timing Diagram (4–Beat Burst)................................................ 10–47
Variable Latency I/O Read Timing (Burst-of-Four, with One Wait
Cycle Per Beat) ............................................................................................. 10–49
Variable Latency I/O Write Timing (Burst-of-Four, with One Wait
Cycle Per Beat) ............................................................................................. 10–50
Flash Write Timing Diagram (2 Writes) ......................................................... 10–51
SMROM State Machine ................................................................................ 10–54
SMROM Eight-Beat and Two-Beat Timing for 2 M x 16 Bit Organization
(32 Mbit) at Half-Memory Clock Frequency (MDREFR:K0DB2=1) ............... 10–55
PCMCIA Memory Map .................................................................................. 10–56
PCMCIA External Logic for a Two-Socket Configuration.............................. 10–59
PCMCIA External Logic for a One-Socket Configuration.............................. 10–60
PCMCIA Memory or I/O 16-Bit Access ......................................................... 10–61
PCMCIA I/O 16-Bit Access to 8-Bit Device ................................................... 10–62
Peripheral Control Module Block Diagram ...................................................... 11–2
Big and Little Endian DMA Transfers .............................................................. 11–8
Palette Buffer Format .................................................................................... 11–18
4 Bits Per Pixel Data Memory Organization (Little Endian)........................... 11–19
8-Bits Per Pixel Data Memory Organization (Little Endian) .......................... 11–20
12-Bits Per Pixel Data Memory Organization (Passive Mode Only) ............. 11–20
16-Bits Per Pixel Data Memory Organization (Active Mode Only) ................ 11–20
LCD Data-Pin Pixel Ordering ........................................................................ 11–27
Frame Buffer/Palette Bits Output to LCD Data Pins in Active Mode............. 11–29
Passive Mode Beginning-of-Frame Timing ................................................... 11–50
Passive Mode End-of-Frame Timing............................................................. 11–51
Passive Mode Pixel Clock and Data Pin Timing ........................................... 11–52
Active Mode Timing....................................................................................... 11–53
Active Mode Pixel Clock and Data Pin Timing .............................................. 11–54
Connecting the USB to the SA-1110 ............................................................ 11–57
NRZI Bit Encoding Example.......................................................................... 11–58
IN, OUT, and SETUP Token Packet Format................................................. 11–60
SOF Token Packet Format ........................................................................... 11–60
Data Packet Format ...................................................................................... 11–60
Handshake Packet Format............................................................................ 11–60
Bulk Transaction Formats ............................................................................. 11–61
Control Transaction Formats......................................................................... 11–62
HP-SIR* Modulation Example ....................................................................... 11–85
UART Frame Format for IrDA Transmission (<= 115.2 Kbps) ...................... 11–86
4PPM Modulation Encodings ........................................................................ 11–86
4PPM Modulation Example........................................................................... 11–87
High-Speed Serial Frame Format for IrDA Transmission (4.0 Mbps) ........... 11–87
Example UART Data Frame ....................................................................... 11–109
MCP Frame Data Format............................................................................ 11–128
MCP Frame Pin Timing............................................................................... 11–128
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SA-1110 Developer’s Manual