SA1110 Datasheet, PDF (157/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Memory and PCMCIA Control Module
10.5.1
ROM Interface Overview
The SA-1110 provides programmable timing for both burst and non-burst ROMs. The RDF field in
MSCx is the latency (in memory clock cycles) for the first and all subsequent data beats from
nonburst ROMs, and the first data beat from a burst ROM. RDN is the latency for the burst data
beats after the first for burst ROMs. RRR delays the following access to a different memory space
to allow time for the current ROM to tristate the data bus. This parameter should be programmed
with the maximum t_OFF value, as specified by the ROM manufacturer. One memory clock cycle is
always added to RDF and RDN. One memory clock cycle is added to RRR if it was set to zero,
otherwise it is doubled. Upon hardware or sleep reset, MSC0 15:0 is initialized such that the RDF,
RDN and RRR fields are set to their maximum values to accommodate the slowest nonburst ROMs
at initial boot, RT is set to be nonburst ROM, and RBW0 is loaded with the value of the inverse of
the ROM_SEL pin. The remaining fields in MSC0, MSC1, and MSC2 are not initialized on
hardware or sleep reset. MSC0 15:0 is selected when the address space corresponding to nCS0 is
accessed.
The SA-1110 supports a ROM burst size of 1, 4 or 8. A single CBR refresh cycle, for asynchronous
DRAM and/or SDRAM, may be inserted between word accesses within a burst transaction. nCS
and nOE are deasserted during the refresh cycle.
10.5.2 ROM Timing Diagrams and Parameters
Figure 10-12, Figure 10-13, and Figure 10-14 show the timing for burst and nonburst ROMS.
Figure 10-12. Burst-of-Eight ROM or Flash Read Timing Diagram
Memory Clock
nCS0
A[25:5]
A[4:2]
nOE
RDF+1.5
RDF+2
0
RDN+1 RDN+1 RDN+1 RDN+1 RDN+1 RDN+1 RDN+1
1
2
3
4
5
6
7
RD/nWR
Input Data
nCS1
Contents of static memory register fields:
MSC0:RDF0=8
MSC0:RDN0=4
max* (2*RRR,1)
MSC0:RRR0=2
A6639-02
SA-1110 Developer’s Manual
10-43