SA1110 Datasheet, PDF (115/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Memory and PCMCIA Control Module 10
The external memory bus interface for the Intel^® StrongARM^* SA-1110 Microprocessor
(SA-1110) supports fast-page-mode (FPM) and extended-data-out (EDO) asynchronous DRAMs,
synchronous DRAM (SDRAM), burst and nonburst ROMs, synchronous mask ROM (SMROM),
burst and nonburst Flash memory, SRAM, PCMCIA expansion memory, and SRAM-like variable
latency I/O devices. It is programmable through the memory interface configuration registers.
Figure 10-1 shows a block diagram of the maximum configuration of the memory controller.
Figure 10-1. General Memory Interface Configuration
nRAS/nSDCS<0>
DRAM Bank 0
nRAS/nSDCS<1>
DRAM Bank 1
nRAS/nSDCS<2>
DRAM Bank 2
Intel^®
StrongARM^®*
SA-1110
Memory
Controller
Interface
nRAS/nSDCS<3>
DRAM Bank 3
nCAS/DQM<3:0>
nSDRAS, nSDCAS,
SDCLK<2:0>, SDCKE<1:0>
D<31:0>
A<25:0>
PCMCIA Control
Dynamic Memory Interface
Up to 4 banks of FPM, EDO, or SDRAM
memory (16-bit or 32-bit wide)
Socket 0
Buffers and
Transceivers ^{Socket 1}
PCMCIA Interface
Up to 2-socket support.
Requires some
external buffering
nCS<0>
nCS<1>
nCS<2>
nCS<3>
nCS<4>
nCS<5>
RDY
Static Bank 0
Static Bank 1
Static Bank 2
Static Memory Interface
Up to 3 banks of ROM, Flash, SRAM or SMROM*
memory (16-bit or 32-bit wide)
NOTE:
Static Bank 0 must be populated by "bootable" memory
Static / Variable Latency I/O Bank 3
Static / Variable Latency I/O Bank 4
Static / Variable Latency I/O Bank 5
Static Memory or
Variable I/O Interface
Up to 3 banks of ROM, Flash,
SMROM** or SRAM-like variable
latency I/O devices
(16-bit or 32-bit wide)
* StrongARM is a registered trademark of ARM Limited.
** SMROM width is required to be 32 bits and it is supported only on nCS<3.0>.
A6624-01
* Other brands and names are the property of their respective owners.
SA-1110 Developer’s Manual
10-1