SA1110 Datasheet, PDF (179/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Memory and PCMCIA Control Module
10.7.2
Software or Watchdog Reset Procedures
Software is responsible for controlling the following procedures when coming out of software or
watchdog reset. They must be completed prior to any SDRAM accesses or writes to MDCNFG or
MDREFR, to ensure that every SDRAM row is precharged prior to receiving the next bank activate
(ACT) or mode register set (MRS) command.
1. Disable all SDRAM banks by clearing MDCNFG:DE3..0, without changing
MDCNFG:DTIM2,0.
2. Trigger a precharge all (PALL) command to SDRAM by attempting a nonburst read or write
access to any disabled DRAM bank.
3. Re-enable SDRAM banks by setting MDCNFG:DE3..0.
10.8
Alternate Memory Bus Master Mode
The SA-1110 supports the existence of an alternate master on the DRAM memory bus. The
alternate master is given control of the bus using a hardware handshake. This handshake is
performed through MBREQ and MBGNT, which are invoked through the alternate functions on
GPIO 22 and GPIO 21 respectively. When the alternate master wants to take control of the memory
bus, it asserts MBREQ (GPIO 22). The SA-1110 will complete any pending or in-progress memory
operation and any outstanding DRAM refresh cycle. It then deasserts SDCKE 1 and tristates all
memory bus pins used with DRAM bank 0 (nRAS/nSDCS 0, A 25:0, nOE, nWE, nSDRAS,
nSDCAS, SDCLK 1, D 31:0, nCAS/DQM 3:0). All other memory and PCMCIA pins remain
driven, including SDCLK 2 is driven to 0 , SDCLK 0 is driven to 0, and SDCKE 0 is driven to 1.
The RD/nWR pin will remain low. After that the SA-1110 will assert MBGNT (GPIO 21), the
alternate master should start driving all pins (including SDCLK 1), and the SA-1110 will re-assert
SDCKE 1. The grant sequence and timing are as follows; the Tmem unit of time is the memory
clock period (twice the CPU clock period):
— Alternate master asserts MBREQ
— SA-1110 deasserts SDCKE 1 at time (t)
— SA-1110 begins to tristate DRAM outputs at time (t + 1*Tmem)
— SA-1110 asserts MBGNT at time (t + 2*Tmem)
— Alternate master begins to drive DRAM outputs prior to time (t + 3*Tmem)
— SA-1110 asserts SDCKE 1 at time (t + 4*Tmem)
During the tristate period, both MBREQ and MBGNT remain high and an external device may take
control of the tristated pins. The external device should drive all the tristated pins even if some are
not actually used. Otherwise, floating inputs may cause excessive crossover current and/or
erroneous SDRAM commands. Note that during the tristate period, the SA-1110 is unable to
perform DRAM refresh cycles. The alternate master must assume the responsibility for DRAM
integrity during this period. It is recommended that the system be designed such that the period of
alternate mastership is limited to much less than the refresh period, or that the alternate master
implement a refresh counter making it capable of performing refresh at the proper intervals.
To give up the bus, the alternate master deasserts MBREQ. The SA-1110 deasserts SDCKE 1 and
deasserts MBGNT, the alternate master stops driving all the DRAM pins (including SDCLK 1), the
SA-1110 resumes driving all DRAM pins (including SDCLK 1), and the SA-1110 re-asserts
SDCKE 1. The release sequence and timing are as follows:
SA-1110 Developer’s Manual
10-65