SA1110 Datasheet, PDF (121/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Memory and PCMCIA Control Module
10.1.2
10.1.3
10.1.4
10.1.5
Types of Memory Accesses
The SA-1110 performs memory accesses for the following operations:
Unbuffered write
Uncached read
Buffered write
Linefetch
Read buffer fetch
Internal DMA write
Level 1 translation fetch
Level 2 translation fetch
Cache line copyback
Read-lock-write sequence
Internal DMA read
SA-1110 will only generate a subset of all possible transactions on the bus. Many of these
transactions may be completed internal to the processor by accessing caches, the read buffer,
on-chip registers, or the special memory space (128 Mbytes starting at physical address
0xE000 0000) that returns zeroes for flushing the cache.
If a memory access is followed by an idle period on the bus, the control signals return to their
inactive state and the address and data signals remain at their previous values to avoid unnecessary
bus transitions and eliminate the need for many pull-up resistors.
Reads
Read bursts are generated by DMA requests, read buffer requests, and cache line fills. All line fills
(for instruction and data caches) are eight words long. DMA and read buffer requests are one, four,
or eight words long. All other reads are single (nonburst) word accesses.
Writes
The write buffer and DMA requests generate single (nonburst) accesses that each write one byte,
one halfword, or one full word. They also generate burst accesses that each write one, two, three, or
four full words. Additionally, cache line castouts can cause the write buffer to generate burst
accesses that each write eight full words.
For stores to DRAM or SRAM memory spaces, the nCAS 3:0 lines enable the corresponding byte
of the data bus during a write transaction. Flash memory space stores must be the width of the
Flash data bus, either 16 or 32 bits.
Transaction Summary
Table 10-1 lists all the transactions that the SA-1110 can generate. No burst will cross an aligned
32-byte boundary. Note that on a 16-bit data bus, each full word access becomes a two half-word
burst, with address bit 1 always starting at 0. Each write access to Flash memory space must take
place in one nonburst operation, regardless of bus size.
SA-1110 Developer’s Manual
10-7