SA1110 Datasheet, PDF (166/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Memory and PCMCIA Control Module
In Figure 10-18 some of the parameters are defined as follows:
tAS = Address setup to nCS = 1 CPU cycle
tCES = nCS setup to nWE = 2 memory clock cycles (4 CPU cycles)
tASW = Address setup to nWE low (asserted) = 2-1/2 memory cycles (5 CPU cycles)
tDSWH = If RT=00, then: Write data setup to nWE high (deasserted) = 1/2 memory cycle +
(RDN+1) memory cycles. If RT=1x, then: Write data setup to nWE high (deasserted) = 1/2
memory cycle + (RDF+1) memory cycles.
tDH = Data hold after nWE high = 1+1/2 memory cycle
tCEH = nCS held asserted after nWE deasserted = 1 memory clock cycle (2 CPU cycles)
tAH = Address hold after nWE deasserted = 1+1/2 memory cycle (3 CPU cycles)
10.5.9
SMROM Overview
The SMROM interface uses thirteen of the DRAM interface’s fifteen multiplexed row/column
address signals (DRA12-0), four static memory chip select signals (nCS 3:0), thirty-two data
signals (D 31:0), a write enable signal (nWE) that should be connected to the SMROM’s MR input,
an output enable signal (nOE), a row address strobe (nSDRAS), a column address strobe
(nSDCAS), a memory clock (SDCLK 0), and a memory clock enable (SDCKE 0).
10.5.10 SMROM Commands
The SA-1110 accesses SMROM by using the following subset of standard interface commands:
• Power-Down (PWRDN)
• Exit Power-Down (PWRDNX)
• Mode Register Set (MRS)
• Row Activate (ACT)
• Read (READ)
• Burst Stop (STOP)
• No Operation (NOP)
Table 10-10 shows the SMROM interface commands.
Table 10-10. SMROM Command Encoding
SA-1110 Pins
Command ^{SDCKE SDCKE}
(at
(at
ncs
clock
clock
3:0
n-1)
n)
PWRDN 1
0
1
PWRDNX 0
1
1
nSDRAS nSDCAS nWE
nOE
1
1
1
1
1
4’b1111
1
4’b1111
MRS
1
x
0
0
0
0
1
ACT
1
x
0
0
1
READ
1
x
0
1
0
1
1
1
0
DRA12-0
x
x
Mode
(DRA 12:7 = 6’b0
DRA 6 = {RL},
DRA 5:3 = {CL}
DRA 2:0 = 3’b010)
Row
Column
10-52
SA-1110 Developer’s Manual