SA1110 Datasheet, PDF (236/406 Pages) Intel Corporation – Intel StrongARM SA-1110 Microprocessor

Peripheral Control Module
11.8.1 USB Operation
Following a reset of the SA-1110 or whenever the UDC is attached to a USB bus, all endpoints are
automatically configured by the UDC and the UDC is forced to use the USB default address of
zero. The host then assigns the UDC a unique address. At this point, the UDC is under the host’s
control and responds to its commands that are transmitted to endpoint 0 using control transactions.
Endpoint 1 is used to perform bulk OUT data transactions, receiving data from the USB host, and
endpoint 2 bulk IN data transactions, transmitting data to the USB host. The following table
defines the UDC Control Register (UDCCR).
Note:
The device that the SA-1110 is implemented in cannot be powered by the USB cable alone. A
bus—powered device model does not function in this instance because when the host sends a
suspend signal, the device is required to consume less than 500uA as per Section 7.2.3 of the USB
specification, Version 1.1. The device cannot limit its current consumption to 500uA unless it
enters sleep mode. When the device enters sleep mode, all UDC registers in the SA-1110 are reset
and will not respond to a host–assigned address.
The following sections provide details of the USB protocol in a bottom-up fashion starting with
signalling levels.
11.8.1.1 Signalling Levels
USB uses differential signalling to encode data and to communicate various bus conditions. The
USB specification refers to the J and K data states to differentiate between high- and low-speed
transmission. Because the UDC supports only 12-Mbps transmission, references are made only to
actual data state 0 and actual data state 1.
Four distinct states are represented using differential data by decoding the polarity of the UDC+
and UDC- pins. Two of the four states are used to represent data. A one is represented when UDC+
is high and UDC- is low; a zero is represented when UDC+ is low and UDC- is high. The
remaining two states and pairings of the four encodings are further decoded to represent the current
state of the USB bus. Table 11-10 shows how seven different bus states are represented using
differential signalling.
Table 11-10. USB Bus States
Bus State
Idle
Resume
Start of Packet
End of Packet
Disconnect
Connect
Reset
UDC+/UDC- Pin Levels
UDC+ high, UDC- low (same as a 1).
UDC+ low, UDC- high (same as a 0).
Transition from idle to resume.
UDC+ AND UDC- low for 2-bit times followed by an idle for 1-bit time.
UDC+ AND UDC- below single-ended low threshold for more than 2.5 µs.
(Disconnect is the static bus condition that results when no device is plugged into a hub
port.)
UDC+ OR UDC- high for more than 2.5 µs.
UDC+ AND UDC- low for more than 2.5 µs. (Reset is driven by the host controller and
sensed by a device controller.)
Hosts and hubs have pull-down resistors on both the D+ and D- lines. When a device is not attached
to the cable, the pull-down resistors cause D+ and D- to be pulled down below the single-ended low
threshold of the host or hub. This creates a state called single-ended zero (SE0). A disconnect is
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SA-1110 Developer’s Manual